參數(shù)資料
型號： V53C806H60
廠商： Mosel Vitelic, Corp.
元件分類： 圓形連接器
英文描述： Circular Connector; Body Material:Aluminum; Series:PT06; Number of Contacts:16; Connector Shell Size:20; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Circular Contact Gender:Pin; Insert Arrangement:20-16
中文描述： 高性能100萬× 8位快速頁面模式的CMOS動態(tài)隨機存儲器
文件頁數(shù)： 15/18頁
文件大小： 135K
代理商： V53C806H60
MOSEL V ITELIC
V53C806H
15
V53C806H Rev. 1.6 April 1998
has no effect on any data stored in the output latch-
es. A WE low level can also disable the output driv-
ers. During a Write cycle, if WE goes low at a time
when the CAS is low, it is necessary to use OE to
disable the output drivers prior to the WE low tran-
sition to allow Data In Setup Time (t
DS
) to be satis-
fied.
To retain data, 1024 Refresh Cycles are required
in each 16 ms period. There are two ways to refresh
the memory:
1.
By clocking each of the 1024 row addresses
(A
0
through A
9
) with RAS at least once every
16 ms. Any Read, Write, Read-Modify-Write or
RAS-only cycle refreshes the addressed row.
Using a CAS-before-RAS Refresh Cycle. If
CAS makes a transition from low to high to low
after the previous cycle and before RAS falls,
CAS-before-RAS refresh is activated. The
V53C806H uses the output of an internal
10-bit counter as the source of row addresses
and ignore external address inputs.
2.
CAS-before-RAS is a “refresh-only” mode and no
data access or device selection is allowed. Thus,
the output remains in the High-Z state during the cy-
cle. A CAS-before-RAS counter test mode is provid-
ed to ensure reliable operation of the internal
refresh counter.
Data Retention Mode
The V53C806H offers a CMOS standby mode
that is entered by causing the RAS clock to swing
between a valid V
IL
and an “extra high” V
IH
within
0.2 V of V
CC
. While the RAS clock is at the extra
high level, the V53C806H power consumption is re-
duced to the low I
CC6
level. Overall I
CC
consump-
tion when operating in this mode can be calculated
as follows:
Where:
t
RC
= Refresh Cycle Time
t
RX
= Refresh Interval/1024
Power-On
After application of the V
CC
supply, an initial
pause of 200
m
s is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the V
CC
current requirement of
the V53C806H is dependent on the input levels of
RAS and CAS. If RAS is low during Power-On, the
device will go into an active cycle and I
CC
will exhibit
current transients. It is recommended that RAS and
CAS track with V
CC
or be held at a valid V
IH
during
Power-On to avoid current surges.
Table 1. V53C806H Data Output
Operation for Various Cycle Types
I
t
-------------------------------------+
(
)
I
(
)
t
t
RX
)
I
CC6
(
)
′
=
Cycle Type
I/O State
Read Cycles
Data from Addressed
Memory Cell
CAS-Controlled Write
Cycle (Early Write)
High-Z
WE-Controlled Write
Cycle (Late Write)
OE Controlled.
High OE = High-Z I/Os
Read-Modify-Write
Cycles
Data from Addressed
Memory Cell
Fast Page Mode Read
Data from Addressed
Memory Cell
Fast Page Mode Write Cycle
(Early Write)
High-Z
Fast Read-Modify-Write
Cycle
Data from Addressed
Memory Cell
RAS-only Refresh
High-Z
CAS-before-RAS
Refresh Cycle
Data remains as in previous
cycles
CAS-only Cycles
High-Z
相關(guān)PDF資料
PDF描述
V53C806H High Performance 1M x 8 Bit Fast Page Mode CMOS Dynamic RAM(高性能1Mx8快速頁面模式CMOS動態(tài)RAM)
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