參數(shù)資料
型號(hào)： V53C517400A
廠商： Mosel Vitelic, Corp.
英文描述： 4M x 4 Fast Page Mode CMOS Dynamic RAM(4Mx4快速頁(yè)面模式CMOS動(dòng)態(tài)RAM)
中文描述： 4米× 4快速頁(yè)面模式的CMOS動(dòng)態(tài)RAM（4Mx4快速頁(yè)面模式的CMOS動(dòng)態(tài)內(nèi)存）
文件頁(yè)數(shù)： 8/28頁(yè)
文件大?。?/td> 186K
代理商： V53C517400A
8
V53C517400A Rev. 1.1 March 1998
MOSEL V ITELIC
V53C517400A
Notes:
1)
All voltages are referenced to V
SS
.
2)
I
CC1
, I
CC3
, I
CC4
and I
CC5
depend on cycle rate.
3)
I
CC1
and I
CC4
depend on output loading. Specified values are obtained with the output open.
4)
Address can be changed once or less while RAS = V
IL
. In case of I
CC4
it can be changed once or less during a Fast
Page mode cycle
5)
An initial pause of 200
m
s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be
a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum
of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6)
AC measurements assume t
T
= 2 ns.
7)
V
IH (min.)
and V
IL (max.)
are reference levels for measuring timing of input signals. Transition times are also measured
between V
IH
and V
IL
.
8)
Measured with the specified current load and 100 pF at V
OL
= 0.8 V and V
OH
= 2.0 V. Access time is determined by
the latter of t
RAC
, t
CAC
, t
CAA
,t
CPA
, t
OEA
. t
CAC
is measured from tristate.
9)
Operation within the t
RCD (max.)
limit ensures that t
RAC (max.)
can be met. t
RCD (max.)
is specified as a reference point
only. If t
RCD
is greater than the specified t
RCD (max.)
limit, then access time is controlled by t
CAC
.
10)
Operation within the t
RAD (max.)
limit ensures that t
RAC (max.)
can be met. t
RAD (max.)
is specified as a reference point
only. If t
RAD
is greater than the specified t
RAD (max.)
limit, then access time is controlled by t
CAA
.
11)
Either t
RCH
or t
RRH
must be satisfied for a read cycle.
12)
t
OFF (max.)
, t
OEZ (max.)
define the time at which the output achieves the open-circuit conditions and are not referenced
to output voltage levels. t
OFF
is referenced from the rising edge of RAS or CAS, whichever occurs last.
13)
Either t
DZC
or t
DZO
must be satisfied.
14)
Either t
CDD
or t
ODD
must be satisfied.
15)
t
WCS
, t
RWD
, t
CWD
and t
AWD
are not restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If t
WCS
> t
WCS (min.)
, the cycle is an early write cycle and data out pin will remain open-circuit
(high impedance) through the entire cycle; if t
RWD
> t
RWD (min.)
, t
CWD
> t
CWD (min.)
and t
AWD
> t
AWD (min.)
, the cycle
is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions
is satisfied, the condition of I/O (at access time) is indeterminate.
16)
These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-
write cycles.
17)
When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh
cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh
interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit
from Self Refresh.
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