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| 型號： | V53C516165A |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 5 Volt 1M X 16 EDO Page Mode CMOS Dynamic RAM(5V 1Mx16 EDO頁面模式CMOS動態(tài)RAM) |
| 中文描述： | 5伏100萬× 16 EDO公司頁面模式的CMOS動態(tài)RAM（5V的1Mx16 EDO公司頁面模式的CMOS動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 7/28頁 |
| 文件大小： | 174K |
| 代理商： | V53C516165A |
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7
V53C516165A Rev. 1.0 March 1998
MOSEL V ITELIC
V53C516165A
Notes:
1. All voltage are referenced to V
SS
.
2.
I
CC1
, I
CC3
, I
CC4
, and I
CC7
depend on cycle rate.
3.
I
CC1
and I
CC4
depend on output loading. Specified values are measured with the output open.
4.
Address can be changed once or less while RAS = V
IL
. In the case of I
CC4
it can be changed once or less during
an EDO cycle (t
HPC
).
5.
An initial pause of 200
μ
s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be
a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of
8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6.
V
IH
(min.) and V
IL
(max.) are reference levels for measuring timing of input signals. Transition times are also mea-
sured between V
IH
and V
IL
.
7.
Measured with a load equivalent to 2 TTL gates and 50 pF (V
OL
= 0.8V and V
OH
= 2.0V).
8.
t
OFF
(max.) and t
OEZ
(max.) define the time at which the outputs acheive the open-circuit condition and are not ref-
erenced to output voltage levels.
9.
Either t
RCH
or t
RRH
must be satisfied for a read cycle.
10.
These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in
read-write cycles.
11.
t
WCS
, t
RWD
, t
CWD
, t
AWD
and t
CPWD
are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If t
WCS
> t
WCS
(min.), the cycle is an early write cycle and the I/O pin will remain open-
circuit (high impedance) through the entire cycle; if t
RWD
> t
RWD
(min.), t
CWD
> t
CWD
(min.), t
AWD
> t
AWD
(min.), and
t
CPWD
> t
CPWD
(min.), the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If
neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate.
12.
Operation within the t
RCD
(max.) limit ensures that t
RAC
(max.) can be met. t
RCD
(max.) is specified as a reference
point only: if t
RCD
is greater than the specified t
RCD
(max.) limit, then access time is controlled by t
CAC
.
13.
Operation within the t
RAD
(max) limit ensures that t
RAC
(max.) can be met. t
RAD
(max.) is specified as a reference
point only: if t
RAD
is greater than the specified t
RAD
(max.) limit, then access time is controlled by t
CAA
.
14.
AC measurements assume t
T
= 2 ns.
15.
Either t
DZC
or t
DEO
must be satisfied.
16.
Either t
CDD
or t
ODD
must be satisfied.
17.
When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM oper-
ation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh
cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR – Distributed/Burst; or CBR – Burst) over the re-
fresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after
exit from Self Refresh.
18.
t
OFF
is referenced from the rising edge of RAS or CAS, whichever occurs last.
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