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| 型號(hào)： | V53C365805A |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 3.3 Volt 8M X 8 EDO Page Mode CMOS Dynamic RAM(3.3V 8Mx8 EDO頁(yè)面模式CMOS動(dòng)態(tài)RAM) |
| 中文描述： | 3.3伏8米× 8 EDO公司頁(yè)面模式的CMOS動(dòng)態(tài)RAM（3.3 8Mx8 EDO公司頁(yè)面模式的CMOS動(dòng)態(tài)內(nèi)存） |
| 文件頁(yè)數(shù)： | 9/24頁(yè) |
| 文件大小： | 158K |
| 代理商： | V53C365805A |
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9
V53C365805A Rev. 1.0 January 1998
MOSEL V ITELIC
V53C365805A
Notes:
1)
All voltages are referenced to VSS.
V
IH
may overshoot to V
CC
+ 0.2V for pulse widths of < 4ns with 3.3V. V
IL
may undershoot to -2.0V for pulse width
< 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
2)
I
CC1
, I
CC3
, I
CC4
and I
CC6
and I
CC7
depend on cycle rate.
3)
I
CC1
and I
CC4
depend on output loading. Specified values are measured with the output open.
4)
Address can be changed once or less while RAS = V
IL
. In the case of I
CC4
it can be changed once or less during a
edo page mode cycle (t
PC
).
5)
An initial pause of 100
m
s is required after power-up followed by 8 RAS-only-refresh cycles, before proper device
operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cy-
cles instead of 8 RAS cycles are required.
6)
AC measurements assume t
T
= 5 ns.
7)
V
IH (min.)
and V
IL (max.)
are reference levels for measuring timing of input signals. Also, transition times are measured
between V
IH
and V
IL
.
8)
Measured with the specified current load and 100 pF at V
OH
= 2.0 V and V
OL
= 0.8 V.
9)
Operation within the t
RCD (max.)
limit ensures that t
RAC (max.)
can be met. t
RCD (max.)
is specified as a reference point
only: If t
RCD
is greater than the specified t
RCD (max.)
limit, then access time is controlled by t
CAC
.
10)
Operation within the t
RAD (max.)
limit ensures that t
RAC (max.)
can be met. t
RAD (max.)
is specified as a reference point
only: If t
RAD
is greater than the specified t
RAD (max.)
limit, then access time is controlled by t
CAA
.
11) Either t
RCH
or t
RRH
must be satisfied for a read cycle.
12) t
OFF (max.)
and t
OEZ (max.)
define the time at which the outputs achieve the open-circuit condition and are not
referenced to output voltage levels.
13) Either t
DZC
or t
DZO
must be satisfied.
14) Either t
CDD
or t
ODD
must be satisfied.
15) t
WCS
, t
RWD
, t
CWD
, t
AWD
and t
CPWD
are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If t
WCS
> t
WCS
(min.), the cycle is an early write cycle and the I/O pin will remain open-
circuit (high impedance) through the entire cycle; if t
RWD
> t
RWD (min.)
, t
CWD
> t
CWD (min.)
, t
AWD
> t
AWD (min.)
and
t
CPWD
> t
CPWD (min.)
, the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If
neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate.
16) These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in Read-
Modify-Write cycles.
17)
In a Test Mode Read Cycle, the value of t
RAC
, t
CAA
, t
CAC
and t
CPA
are delayed by 5 ns from the specified value.
These parameters must be adjusted in Test Mode cycles by adding 5ns to the specified value. Associated timings
must be adjusted by 5 ns.
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