參數(shù)資料
型號(hào): V437316S04V
廠商: Mosel Vitelic, Corp.
英文描述: 3.3 VOLT 16M x 72 HIGH PERFORMANCE UNBUFFERED ECC SDRAM MODULE
中文描述: 3.3伏16米x 72高性能無(wú)緩沖ECC內(nèi)存模塊
文件頁(yè)數(shù): 8/12頁(yè)
文件大?。?/td> 338K
代理商: V437316S04V
8
V437316S04V Rev. 1.0 December 2001
MOSEL VITELIC
V437316S04V
5
t
CL
Clock Low Pulse Width
2.5
2.5
2.5
ns
6
t
T
Transition Tim
1
1
1
ns
Setup and Hold Times
7
t
IS
Input Setup Time
1.5
1.5
1.5
ns
5
8
t
IH
Input Hold Time
0.8
0.8
0.8
ns
5
9
t
CKS
Input Setup Time
1.5
1.5
1.5
ns
5
10
t
CKH
CKE Hold Time
0.8
0.8
0.8
ns
5
11
t
RSC
Mode Register Set-up Time
15
15
15
ns
12
t
SB
Power Down Mode Entry Time
0
7.5
0
7.5
0
7.5
ns
Common Parameters
13
t
RCD
Row to Column Delay Time
15
20
20
ns
6
14
t
RP
Row Precharge Time
20
20
20
ns
6
15
t
RAS
Row Active Time
42
100K
45
100K
45
100K
ns
6
16
t
RC
Row Cycle Time
60
70
70
ns
6
17
t
RRD
Activate(a) to Activate(b) Command
Period
14
15
20
ns
6
18
t
CCD
CAS(a) to CAS(b) Command Period
1
1
1
CLK
Refresh Cycle
19
t
REF
Refresh Period (4096 cycles)
64
64
64
ms
20
t
SREX
Self Refresh Exit Time
10
10
10
ns
Read Cycle
21
t
OH
Data Out Hold Time
3
3
3
ns
2
22
t
LZ
Data Out to Low Impedance Time
0
0
0
ns
23
t
HZ
Data Out to High Impedance Time
3
7.5
3
7.5
3
8
ns
7
24
t
DQZ
DQM Data Out Disable Latency
2
2
2
CLK
Write Cycle
25
t
WR
Write Recovery Time
2
2
1
CLK
26
t
DQW
DQM Write Mask Latency
0
0
0
CLK
AC Characteristics
T
A
= 0
°
to 70
°
C; V
SS
= 0V; V
CC
= 3.3V
±
0.3V, t
T
= 1 ns (Continued)
#
Symbol
Parameter
Limit Values
Unit
Note
-75PC
-75
-10PC
Min.
Max.
Min.
Max.
Min.
Max.
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