參數(shù)資料
型號(hào): V436516Y04VATG-10PC
廠商: Mosel Vitelic, Corp.
英文描述: 128MB 144-PIN UNBUFFERED SDRAM SODIMM, 16MX64 3.3VOLT
中文描述: 128MB的144引腳無(wú)緩沖內(nèi)存的SODIMM,16MX64 3.3VOLT
文件頁(yè)數(shù): 8/11頁(yè)
文件大?。?/td> 307K
代理商: V436516Y04VATG-10PC
8
V436516Y04V Rev. 1.0 October 2001
MOSEL VITELIC
V436516Y04V
Notes:
1.
The specified values are valid when addresses are changed no more than once during t
CK
(min.) and when No
Operation commands are registered on every rising clock edge during t
RC
(min). Values are shown per module
bank.
2.
The specified values are valid when data inputs (DQ
s) are stable during t
RC
(min.).
3.
All AC characteristics are shown for device level.
An initial pause of 100
μ
s is required after power-up, then a Precharge All Banks command must be given followed
by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.
4.
AC timing tests have V
IL
= 0.4V and V
IH
= 2.4V with the timing referenced to the 1.4V crossover point. The transition
time is measured between V
IH
and V
IL
. All AC measurements assume t
T
= 1 ns with the AC output load circuit
shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with
a input signal of 1V / ns edge rate between 0.8V and 2.0V.
Read Cycle
21
t
OH
Data Out Hold Time
2.7
2.7
2.7
ns
2
22
t
LZ
Data Out to Low Impedance Time
1
1
1
ns
23
t
HZ
Data Out to High Impedance Time
5.4
5.4
5.4
ns
7
24
t
DQZ
DQM Data Out Disable Latency
2
2
2
CLK
Write Cycle
25
t
WR
Write Recovery Time
1
1
1
CLK
26
t
DQW
DQM Write Mask Latency
0
0
0
CLK
AC Characteristics
T
A
= 0
°
to 70
°
C; V
SS
= 0V; V
CC
= 3.3V
±
0.3V, t
T
= 1 ns (Continued)
#
Symbol
Parameter
Limit Values
Unit
Note
-75PC
-75
-10PC
Min.
Max.
Min.
Max.
Min.
Max.
1.4V
1.4V
tSETUP
tHOLD
tAC
tAC
tLZ
tOH
tHZ
CLOCK
INPUT
OUTPUT
50 pF
I/O
Z=50 Ohm
+ 1.4 V
50 Ohm
2.4V
0.4V
t
T
tCL
tCH
I/O
Measurement conditions for
tac and toh
50 pF
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