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| 型號： | V375A2C100A3L |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 178K |
| 代理商： | V375A2C100A3L |
+Sense from
other modules
in the array
+In
PC
PR
–
In
+Out
+S
SC
–
Out
–
S
Figure 12
—OR’ing diodes connections.
+Out
+S
SC
–
S
–
Out
+Out
+S
SC
–
S
–
Out
+Out
+S
SC
–
S
–
Out
Load
+S
–
S
+S
–
S
+S
–
S
Module
2
Module
1
+In
PC
PR
–
In
+In
PC
PR
–
In
Module
N+1
+In
PC
PR
–
In
Figure 11
—N+1 module array output connections.
CONTROL FUNCTIONS - PR PIN
Parallel Operation
The PR pin supports paralleling for increased power with N+1
(N+M) redundancy and phased array capability. Modules of the
same input voltage, output voltage, and power level will cur-
rent share if all PR pins are suitably interfaced.
Compatible interface architectures include the following:
DC coupled single-wire interface.
All PR pins are directly
connected to one another. This interface supports current
sharing but is not fault tolerant. Minus In pins must be tied to
the same electric potential. See Figure 9.
AC coupled single-wire interface.
All PR pins are connected to
a single communication bus through
.
001μF (500V) capacitors.
This interface supports current sharing and is fault tolerant
except for the communication bus. See Figure 10.
Vicor Corporation
Tel: 800-735-6200 978-470-2900 Fax: 978-475-6715
Page 6 of 8
The latest data sheets for individual models are available on the Vicor website at www.vicr.com
Figure 9
—DC coupled single-wire interface.
Module 2
(up to 12)
Module
1
Ground plane
+Out
+S
SC
–
S
–
Out
+In
PC
PR
–
In
+Out
+S
SC
–
S
–
Out
+In
PC
PR
–
In
Module 2
(up to 12)
Module
1
Ground plane
+Out
+S
SC
–
S
–
Out
+In
PC
PR
–
In
+Out
+S
SC
–
S
–
Out
+In
PC
PR
–
In
Figure 10
—AC coupled single-wire interface.
.001μF
.001μF
The +Out and
–
Out power buses
should be designed to minimize
and balance parasitic impedance
from each module output to the
load.
The +Sense pins should be tied
to the same point on the +Out
power bus; the
–
Sense pins
should be tied to the same point
on the
–
Out power bus.
At the discretion of the power
system designer, a subset of all
modules within an array may be
configured as slaves by shorting
SC to
–
S.
OR
’
ing diodes may be inserted in
series with the +Out pins of each
module to provide
module output fault tolerance.
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