參數(shù)資料
型號(hào): V29C31001B-70P
廠商: Mosel Vitelic, Corp.
英文描述: 1 MEGABIT 131,072 x 8 BIT 5 VOLT CMOS FLASH MEMORY
中文描述: 1兆131072 × 8位5伏的CMOS閃存
文件頁(yè)數(shù): 1/16頁(yè)
文件大?。?/td> 89K
代理商: V29C31001B-70P
MOSEL V ITELIC
1
V29C51001T/V29C51001B
1 MEGABIT (131,072 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
PRELIMINARY
V29C51001T/V29C51001B Rev. 0.8 October 2000
Features
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128Kx8-bit Organization
Address Access Time: 45, 70, 90 ns
Single 5V
±
10% Power Supply
Sector Erase Mode Operation
8KB Boot Block (lockable)
512 bytes per Sector, 256 Sectors
– Sector-Erase Cycle Time: 10ms (Max)
– Byte-Program Cycle Time: 20
Minimum 10,000 Erase-Program Cycles
Low power dissipation
– Active Read Current: 20mA (Typ)
– Active Program Current: 30mA (Typ)
– Standby Current: 100
Hardware Data Protection
Low V
CC
Program Inhibit Below 2.5V
Self-timed program/erase operations with end-
of-cycle detection
– DATA Polling
– Toggle Bit
CMOS and TTL Interface
Available in two versions
– V29C51001T (Top Boot Block)
– V29C51001B (Bottom Boot Block)
Packages:
– 32-pin Plastic DIP
– 32-pin TSOP-I
– 32-pin PLCC
μ
s (Max)
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μ
A (Max)
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Description
The V29C51001T/V29C51001B is a high speed
131,072 x 8 bit CMOS flash memory. Programming
or erasing the device is done with a single 5 Volt
power supply. The device has separate chip enable
CE, program enable WE, and output enable OE
controls to eliminate bus contention.
The V29C51001T/V29C51001B offers a combi-
nation of features: Boot Block with Sector Erase
Mode. The end of program/erase cycle is detected
by DATA Polling of I/O
7
or by the Toggle Bit I/O
The V29C51001T/V29C51001B features a
sector erase operation which allows each sector to
be erased and reprogrammed without affecting
data stored in other sectors. The device also
supports full chip erase.
Boot block architecture enables the device to
boot from a protected sector loaded either at the
top (V29C51001T) or the bottom (V29C51001B)
sector. All inputs and outputs are CMOS and TTL
compatible.
The V29C51001T/V29C51001B is ideal for
applications that require updatable code and data
storage.
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Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
P
T
J
45
70
90
Std.
0
°
C to 70
°
C
Blank
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