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參數(shù)資料
| 型號(hào)： | V23818K305V10 |
| 英文描述： | FIBER OPTIC TRANSCEIVER |
| 中文描述： | 光纖收發(fā)器 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 1007K |
| 代理商： | V23818K305V10 |
Fiber Optics
V23814/15-K1306-M230 Parallel Optical Link: PAROLI
Tx/Rx DC
5
SCI Mode
§
. Maximum Input Skew=(2*Data Rate)
–
1
–
250 ps
–
DCD
IN-CLOCK
where DCD
IN-CLOCK
=
|
(Data Rate)
–
1
–
dcd*(
1
/
2
Data Rate)
–
1
|
(dcd: see
Recommended Operating Conditions).
Note
1. See Measurement Conventions (Figure 6).
Reset Timing Diagram
Notes
1. Valid after the release of -RESET. (Clock input must first be stable.
Keep -RESET low until clock input is at stable frequency.)
2. Only when not used as power-on reset (see start-up procedure for
power-on reset). At any failure recovery, -RESET should be brought
to low level for at least t
3
.
Figure 6. Measurement conventions for LVDS signals
Setup and Hold Times
Setup and hold times are measured between the cross point of positive
and negative clock and the points where rising and falling data edge
cross the borders of the V-range.
Figure 7. Numbering conventions transmitter
The numbering conventions for the Tx and Rx modules are the same.
Transmitter Pin Description
Pin#
Pin Name
Parameter
Input Skew
(1)
Symbol
Min. Typ.
Max.
Units
t
S
§
ps
Parameter
-RESET On Delay Time
(1)
Symbol Min. Typ. Max.
Units
t
1
t
2
t
3
100
ms
-RESET Off Delay Time
-RESET Low Duration
(2)
50
μs
100
μs
tS
tS
Data Out 1...22
Clock Out
P
N
|V
ID
| min.
3.0 V
V
CC
Data
data invalid
data valid
0.8 V
3.6 V
-RESET
2.0 V
t3
t2
t1
t
SETUP
t
HOLD
Data
Clock
P
N
|V
ID
| min.
Level/Logic
Description
1
V
CC1
Power supply voltage of
laser driver
2
t.b.l.o.
to be left open
3
4
5
6
LCU
LVCMOS
Out
Laser Controller Up
High=laser controller is
operational
Low=laser fault condition if
-RESET is High and
V
CC
is > 3.0 V
Ground
7
V
EE
V
EE
V
CC3
8
Ground
9
Power supply voltage of digi-
tal circuitry and PLL
10
MU
LVCMOS
Out
Module Up
High=normal operation
Low=laser fault or PLL not
locked or -RESET low
11
CIN
LVDS In
Clock Input, inverted
12
CIP
LVDS In
Clock Input, non-inverted
13
DI01N
LVDS In
Data Input #1, inverted
14
DI01P
LVDS In
Data Input #1, non-inverted
15
DI12N
LVDS In
Data Input #12, inverted
16
DI12P
LVDS In
Data Input #12, non-inverted
17
DI02N
LVDS In
Data Input #2, inverted
18
DI02P
LVDS In
Data Input #2, non-inverted
19
DI13N
LVDS In
Data Input #13, inverted
20
DI13P
LVDS In
Data Input #13, non-inverted
21
DI03N
LVDS In
Data Input #3, inverted
22
DI03P
LVDS In
Data Input #3, non-inverted
23
DI14N
LVDS In
Data Input #14, inverted
24
DI14P
LVDS In
Data Input #14, non-inverted
25
V
CC3
Power supply voltage of digi-
tal circuitry and PLL
26
DI04N
LVDS In
Data Input #4, inverted
27
DI04P
LVDS In
Data Input #4, non-inverted
28
V
EE
DI15N
Ground
29
LVDS In
Data Input #15, inverted
30
DI15P
LVDS In
Data Input #15, non-inverted
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