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參數(shù)資料
| 型號： | V104YLF |
| 英文描述： | 10 BIT LVDS RECEIVER FOR VIDEO |
| 中文描述： | 10位LVDS接收機視頻 |
| 文件頁數(shù)： | 3/11頁 |
| 文件大小： | 205K |
| 代理商： | V104YLF |
10 B
IT
LVDS R
ECEIVER
FOR
V
IDEO
V104
V104 Datasheet
3
1/12/05
Revision 1.6
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
PRELIMINARY
**Rxn
x = A, B, C, D, E
n = 0, 1, 2, 3, 4, 5, 6
6, 7, 8, 10, 11,
12, 13
RE6 ~ RE0
OUT
CMOS/TTL Data Outputs.
2
TEST
IN
Not used. Tie LOW.
3
PD
IN
HIGH: normal operation; LOW: Power down (all outputs are “L”).
4
OE
IN
HIGH: Output enable (normal operation); LOW: Output disable (all outputs
are high impedance).
5
R/F
IN
Output Clock triggering edge select. High: Rising edge; Low: Falling edge.
9, 23, 37, 48
VCC
Power
Power supply pins for TTL outputs and digital circuitry.
31
CLKOUT
OUT
Clock out.
1, 16, 30, 44
GND
Ground
Ground pins for TTL outputs and digital circuitry.
53
LVCC
Power
Power supply pins for LVDS inputs.
58
LGND
Ground
Ground pins for LVDS inputs.
64
PVCC
Power
Power supply pin for PLL circuitry.
63
PGND
Ground
Ground pin for PLL circuitry.
Pin
Number
Pin
Name
Pin Type
Pin Description
PD
R/F
OE
Data Outputs (Rxn)
CLKOUT
0
0
0
High impedance
High impedance
0
0
1
All 0
Fixed Low
0
1
0
High impedance
High impedance
0
1
1
All 0
Fixed Low
1
0
0
High impedance
High impedance
1
0
1
Data Out
Latches output data on falling edge
1
1
0
High impedance
High impedance
1
1
1
Data Out
Latches output data on rising edge
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