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參數(shù)資料
| 型號： | UT7R995C-XCX |
| 廠商： | Aeroflex Inc. |
| 英文描述： | RadHard 2.5V/3.3V 200MHz High-Speed Multi-phase PLL Clock Buffer |
| 中文描述： | RadHard 2.5V/3.3V的200MHz的高速多相PLL時鐘緩沖器 |
| 文件頁數(shù)： | 8/22頁 |
| 文件大小： | 185K |
| 代理商： | UT7R995C-XCX |
8
3
sOE
I
LVTTL
Synchronous Output Enable.
The sOE input is used to synchronously enable/
disable the output clocks. Each clock output that is controlled by the sOE pin is
synchronously enabled/disabled by the individual output clock. When
HIGH
, sOE
disables all clocks except 2Q0 and 2Q1. When disabled, 1Q0, 1Q1, 3Q0, and 3Q1
will always enter a
LOW
state when PE/HD is
MID
or
HIGH
, and they will disable
into a
HIGH
state when PE/HD is
LOW
.
The disabled state of 4Q0 and 4Q1 is dependent upon the state of PE/HD and 4F[1:0].
The following table illustrates the disabled state of bank 4 outputs as they are
controlled by the state of PE/HD and 4F[1:0].
PE/HD
LOW
MID
HIGH
*All other combinations of 4F[1:0] will result in 4Q0 and 4Q1 disabling into
a
LOW
state when PE/HD is
MID
or
HIGH
, and they will disable into a
HIGH
state when PE/HD is
LOW
.
4F[1:0]*
HH
HH
HH
4Q0
LOW
HIGH
HIGH
4Q1
LOW
HIGH
HIGH
When TEST is held at the
MID
level and sOE is
HIGH
, the nF[1:0] pins act as
individual output enable/disable controls for each output bank, excluding bank 2.
Setting both nF[1:0] signals
LOW
disables the corresponding output bank.
Set sOE
LOW
to place the UT7R995/C RadClock
TM
outputs into their normal
operating modes.
1, 2, 24,
25, 26, 27,
47, 48
nF[1:0]
I
3-Level
Output divider and phase skew selection for each output bank.
Please see Tables 3, 4, 5, 6, and 9 for a complete explanation of the nF[1:0] control
functions and their effects on output frequency and skew.
46
FS
I
3-Level
VCO operating frequency range selection.
Please see Tables 7 and 8.
8, 9, 17,
18, 31, 32,
41, 42
nQ[1:0]
O
LVTTL
Four clock banks of two outputs each.
Please see Table 6 for frequency settings and Table 9 for skew settings.
22, 23
DS[1:0]
I
3-Level
Feedback input divider selection.
Please see Table 1 for a summary of the feedback input divider settings.
5
PE/HD
I
3-Level
Positive/negative edge control and high/low output drive strength selection.
The
PE portion of this pin controls which edge of the reference input synchronizes the
clock outputs. The HD portion of this pin controls the drive strength of the output
clock buffers. The following table summarizes the effects of the PE/HD pin during
normal operation.
PE/HD
LOW
MID
HIGH
Synchronization
Negative Edge
Positive Edge
Positive Edge
Output Drive Strength
Low Drive
High Drive
Low Drive
Low drive strength outputs provide 12mA of drive strength while the high drive
condition results in 24mA of current drive. Output banks operating from a 2.5V
power supply guarantee a high drive of 20mA.
Flatpack
Pin No.
Name
I/O
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UT7R995C-XPA | RadHard 2.5V/3.3V 200MHz High-Speed Multi-phase PLL Clock Buffer |
| UT7R995C-XPC | RadHard 2.5V/3.3V 200MHz High-Speed Multi-phase PLL Clock Buffer |
| UT7R995C-XPX | RadHard 2.5V/3.3V 200MHz High-Speed Multi-phase PLL Clock Buffer |
| UT7R995C-XWA | RadHard 2.5V/3.3V 200MHz High-Speed Multi-phase PLL Clock Buffer |
| UT7R995C-XWC | RadHard 2.5V/3.3V 200MHz High-Speed Multi-phase PLL Clock Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UT7R995C-XPA | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:RadHard 2.5V/3.3V 200MHz High-Speed Multi-phase PLL Clock Buffer |
| UT7R995C-XPC | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:RadHard 2.5V/3.3V 200MHz High-Speed Multi-phase PLL Clock Buffer |
| UT7R995C-XPX | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:RadHard 2.5V/3.3V 200MHz High-Speed Multi-phase PLL Clock Buffer |
| UT7R995C-XWA | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:RadHard 2.5V/3.3V 200MHz High-Speed Multi-phase PLL Clock Buffer |
| UT7R995C-XWC | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:RadHard 2.5V/3.3V 200MHz High-Speed Multi-phase PLL Clock Buffer |
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