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參數(shù)資料
| 型號： | UT7R995-XWX |
| 廠商： | Aeroflex Inc. |
| 英文描述： | RadHard 2.5V/3.3V 200MHz High-Speed Multi-phase PLL Clock Buffer |
| 中文描述： | RadHard 2.5V/3.3V的200MHz的高速多相PLL時鐘緩沖器 |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 185K |
| 代理商： | UT7R995-XWX |
5
Notes:
1. nF[1:0] = LL disables bank specific outputs if TEST=MID and sOE = HIGH.
2. When TEST=MID or HIGH, the Divide-by-2, Divide-by-4, and Inversion-
options function as defined in Table 9.
3. When 4Q[1:0] are set to run inverted (4F[1:0] = HH), sOE disables these out-
puts HIGH when PE/HD = HIGH or MID, sOE disables them LOW when
PE/HD = LOW.
4. Skew accuracy is within +/- 15% of n*t
U
where "n" is the selected number
of skew steps. Supplied as a design limit, but not tested or guaranteed.
A graphical summary of Table 10 is shown in Figure 3. The
drawing assumes that the FB input is driven by a clock output
programmed with zero skew. Depending upon the state of the
nF[1:0] pins the respective clocks will be skewed, divided, or
inverted relative to the fedback output as shown in Figure 3.
1.3 Output Drive, Synchronization, and Power Supplies:
The UT7R995/C employs flexible output buffers providing the
user with selectable drive strengths, independent power sup-
plies, and synchronization to either edge of the reference input.
Using the 3-level PE/HD pin, the user selects the reference edge
synchronization and the output drive strength for all clock out-
puts. The options for edge synchronization and output drive
strength selected by the PE/HD pin are listed in Table 11.
Notes:
1. Please refer to "DC Parameters" section for I
OH
/I
OL
specifications.
Table 10: Output Skew Settings
4
nF[1:0]
Skew
1Q[1:0], 2Q[1:0]
Skew
3Q[1:0]
Skew
4Q[1:0]
LL
1, 2
-4t
U
Divide by 2
Divide by 2
LM
-3t
U
-6t
U
-6t
U
LH
-2t
U
-4t
U
-4t
U
ML
-1t
U
-2t
U
-2t
U
MM
Zero Skew
Zero Skew
Zero Skew
MH
+1t
U
+2t
U
+2t
U
HL
+2t
U
+4t
U
+4t
U
HM
+3t
U
+6t
U
+6t
U
HH
2
+4t
U
Divide by 4
Inverted
3
Table 11: PE/HD Settings
PE/HD
Synchronization
Output Drive
Strength
1
L
Negative
Low Drive
M
Positive
High Drive
H
Positive
Low Drive
t
0
t
0
U
t
0
U
t
0
U
t
0
U
t
0
U
t
0
U
t
0
U
t
0
U
t
0
U
t
0
U
t
0
U
t
0
U
XTAL1 Input
FB Input
-6t
U
-4t
U
-3t
U
-2t
U
-1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
+6t
U
DIVIDED
INVERTED
1F[1:0]
2F[1:0]
3F[1:0]
4F[1:0]
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
LM
LH
(N/A)
ML
(N/A)
MM
(N/A)
MH
(N/A)
HL
HM
LM
LH
(N/A)
ML
(N/A)
MM
(N/A)
MH
(N/A)
HL
HM
(N/A)
(N/A)
LL/HH
LL
(N/A)
(N/A)
(N/A)
HH
Figure 3. Typical Outputs with FB Connected to a Zero-Skewed Output
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