參數(shù)資料
型號: UT7C139C55WPC
英文描述: x9 Dual-Port SRAM
中文描述: X9熱賣雙端口SRAM
文件頁數(shù): 8/21頁
文件大?。?/td> 272K
代理商: UT7C139C55WPC
8
Figure 3b. Read Cycle 2
CE
OE
Data Out
t
LZCE
t
LZOE
t
DOE
t
ACE
t
HZOE
t
HZCE
Figure 3c. Read Timing with Port-to-Port Delay
Address
R/W
R
Data
INR
Address
L
DATA
OUTL
t
WC
MATCH
t
PWE
t
SD
VALID
t
HD
MATCH
VALID
t
DDD
t
WDD
Assumptions:
1. Address valid prior to or coincident with CE transition LOW
2. R/W is HIGH for read cycle
Assumptions:
1. BUSY = HIGH for the writing port
2. CE
L
= CE
R
= LOW
Address
Data Out
Figure 3a. Read Cycle 1
t
RC
t
OHA
t
AA
Data Valid
Assumptions:
1.R/W is HIGH for read cycle
2.Device is continuously selected CE=LOW and OE=LOW
Previous Data Valid
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