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參數(shù)資料
| 型號(hào)： | UT7C138C55GCA |
| 英文描述： | SRAM|4KX8|CMOS| RAD HARD|PGA|68PIN|CERAMIC |
| 中文描述： | 靜態(tài)存儲(chǔ)器| 4KX8 |的CMOS | RAD數(shù)據(jù)通信硬|美巡賽| 68PIN |陶瓷 |
| 文件頁(yè)數(shù)： | 10/21頁(yè) |
| 文件大?。?/td> | 272K |
| 代理商： | UT7C138C55GCA |
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10
Address
CE
R/W
Data in
OE
Data out
t
WC
t
SCE
t
AW
t
PWE
t
HA
t
SA
t
SD
t
HZOE
t
LZOE
DATA
VALID
HIGH
IMPEDANCE
t
HD
Assumptions:
1. The internal write time of memory is defined by the overlap of CE
LOW and R/W LOW. Both signals must be LOW to initiate a write,
and either signal can terminate a write by going HIGH. The data input
set-up and hold timing should be referenced to the rising edge of the
signal that terminates the write.
2. If OE is LOW during a R/W controlled write cycle, the write pulse
width must be the larger of t
PWE
or (t
HZWE
+ t
SD
) to allow the I/O
drivers to turn off and data to be placed on the bus for the required t
SD
.
If OE is HIGH during a R/W controlled write cycle (as in this exam-
ple), this requirement does not apply and the write pulse can be as
short as the specified t
PWE
.
3. R/W must be HIGH during all address transactions.
Figure 4a. Write Cycle 1: OE Three-States Data I/Os (Either Port)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UT7C138C55GCC | SRAM|4KX8|CMOS| RAD HARD|PGA|68PIN|CERAMIC |
| UT7C138C55GCX | SRAM|4KX8|CMOS| RAD HARD|PGA|68PIN|CERAMIC |
| UT7C138C55GPA | x8 Dual-Port SRAM |
| UT7C139C55GPA | x9 Dual-Port SRAM |
| UT7C139C55GPC | x9 Dual-Port SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UT7C138C55GCC | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:SRAM|4KX8|CMOS| RAD HARD|PGA|68PIN|CERAMIC |
| UT7C138C55GCX | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:SRAM|4KX8|CMOS| RAD HARD|PGA|68PIN|CERAMIC |
| UT7C138C55GPA | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:x8 Dual-Port SRAM |
| UT7C138C55GPC | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:x8 Dual-Port SRAM |
| UT7C138C55GPX | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:x8 Dual-Port SRAM |
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