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參數(shù)資料
| 型號： | UT7C138C45GPA |
| 英文描述： | x8 Dual-Port SRAM |
| 中文描述： | x8雙端口SRAM |
| 文件頁數(shù)： | 12/21頁 |
| 文件大?。?/td> | 272K |
| 代理商： | UT7C138C45GPA |
12
AC CHARACTERISTICS BUSY CYCLE
1
(V
DD
= 5.0V±10%)
Notes:
1. Test conditions assume signal transition time of 5ns or less, timing reference levels of V
DD
/2, input pulse levels of 0.5V to V
DD
-0.5V, and output
loading of the specified I
OL
/I
OH
and 50-pF load capacitance.
2. Violation of t
PS
(with addresses matching) results in at least one of the two busy output signals asserting, only one port remains busy.
3. When violating t
PS
, the busy signal asserts on one port or the other; there is no guarantee on which port the busy signal asserts.
SYMBOL
PARAMETER
7C138 - 45
7C139 - 45
MIN MAX
7C138 - 55
7C139 - 55
MIN MAX
UNIT
t
BLA
BUSY LOW from address match
25
30
ns
t
BZA
BUSY HIGH-Z from address mismatch
25
30
ns
t
BLC
BUSY LOW from CE LOW
25
30
ns
t
BZC
BUSY HIGH from CE HIGH
25
30
ns
t
PS2,3
Port set-up for priority
5
5
ns
t
WB
R/W LOW after BUSY LOW
0
0
ns
t
WH
R/W HIGH after BUSY HIGH
40
50
ns
t
BDD
BUSY HIGH to data valid
45
55
ns
相關PDF資料 |
PDF描述 |
|---|---|
| UT7C138C45GPC | x8 Dual-Port SRAM |
| UT7C138C45GPX | x8 Dual-Port SRAM |
| UT7C138C45WCA | SRAM|4KX8|CMOS| RAD HARD|QFL|68PIN|CERAMIC |
| UT7C138C45WCC | SRAM|4KX8|CMOS| RAD HARD|QFL|68PIN|CERAMIC |
| UT7C138C45WCX | SRAM|4KX8|CMOS| RAD HARD|QFL|68PIN|CERAMIC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| UT7C138C45GPC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
| UT7C138C45GPX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
| UT7C138C45WCA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM|4KX8|CMOS| RAD HARD|QFL|68PIN|CERAMIC |
| UT7C138C45WCC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM|4KX8|CMOS| RAD HARD|QFL|68PIN|CERAMIC |
| UT7C138C45WCX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM|4KX8|CMOS| RAD HARD|QFL|68PIN|CERAMIC |
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