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參數(shù)資料
| 型號(hào)： | UT62L25616I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256K X 16 BIT LOW POWER CMOS SRAM |
| 中文描述： | 256 × 16位低功耗CMOS SRAM |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 203K |
| 代理商： | UT62L25616I |
UTRON
UT62L25616(I)
Rev. 1.1
256K X 16 BIT LOW POWER CMOS SRAM
WRITE CYCLE 1
(
WE
Controlled)
(1,2,3,5)
t
WC
UTRON TECHNOLOGY INC. P80054
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6
t
AW
t
CW
t
AS
t
WP
t
BW
t
WHZ
t
OW
t
DW
t
DH
t
WR
Address
CE
WE
LB , UB
Dout
Din
Data Valid
High-Z
(4)
(4)
WRITE CYCLE 2
(
CE
Controlled)
(1,2,5)
t
WC
t
AW
t
CW
t
AS
t
WR
t
WP
t
BW
t
WHZ
t
DW
t
DH
Data Valid
Address
CE
WE
LB , UB
Dout
Din
High-Z
Notes :
1.
WE
or CE must be HIGH during all address transitions.
2. A write occurs during the overlap of a low CE and a low
WE
.
3. During a
WE
controlled with write cycle with OE LOW, t
WP
must be greater than t
WHZ
+t
DW
to allow the drivers to turn off and data
to be placed on the bus.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
CE
LOW
transition occurs simultaneously with or after
WE
LOW
transition, the outputs remain in a
high impedance state.
6. t
OW
and t
WHZ
are specified with C
L
= 5pF. Transition is measured
±
500mV from steady state.
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| UT62L25616MC-55LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256K X 16 BIT LOW POWER CMOS SRAM |
| UT62L25616MC-55LLI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256K X 16 BIT LOW POWER CMOS SRAM |
| UT62L25616MC-70LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256K X 16 BIT LOW POWER CMOS SRAM |
| UT62L25616MC-70LLI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256K X 16 BIT LOW POWER CMOS SRAM |
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