參數(shù)資料
型號(hào): UT6264C(E)
英文描述: 4 Mb (512K x 8, 256K x 16) Boot Sector, Flash Memory
中文描述: 異步靜態(tài)RAM高速
文件頁(yè)數(shù): 7/13頁(yè)
文件大小: 132K
代理商: UT6264C(E)
UTRON
UT6264C
Rev. 1.4
8K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
FEATURES
Access time : 35/70ns (max.)
Low power consumption :
Operating : 40/30 mA (typ.)
CMOS Standby : 0.3mA (typ.) normal
2
A (typ.) L-version
1
A (typ.) LL-version
Single 4.5V~5.5V power supply
Operating temperature :
Commercial : 0J ~70J
Extended : -20J ~85J
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
8K X 8
MEMORY
ARRAY
COLUMN I/O
OE
WE
A0-A12
Vcc
Vss
I/O1-I/O8
CE
CE2
GENERAL DESCRIPTION
The UT6264C is a 65,536-bit low power CMOS static
random access memory organized as 8,192 words by
8 bits. It is fabricated using high performance, high
reliability CMOS technology.
Easy memory expansion is provided by using two
chip enable input.( CE ,CE2) ,and supports low data
retention voltage for battery back-up operation with
low data retention current.
The UT6264C operates from a single 4.5V~5.5V
power supply and all inputs and outputs are fully TTL
compatible.
PIN CONFIGURATION
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
Vcc
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
UT6264C
PDIP/SOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
CE
WE
OE
CE2
NC
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0 - A12
Address Inputs
I/O1 - I/O8
Data Inputs/Outputs
CE ,CE2
Chip Enable Inputs
WE
Write Enable Input
OE
Output Enable Input
VCC
Power Supply
VSS
Ground
NC
No connection
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