
UTRON
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.0
CAPACITANCE
(TA=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V±10% , TA = 0
℃
to 70
℃
)
(1) READ CYCLE
PARAMETER
SYMBOL
Read Cycle Time
t
RC
Address Access Time
t
AA
Chip Enable Access Time
t
ACE
Output Enable Access Time
t
OE
Chip Enable to Output in Low Z
t
CLZ*
Output Enable to Output in Low Z
t
OLZ*
Chip Disable to Output in High Z
t
CHZ*
Output Disable to Output in High Z
t
OHZ*
Output Hold from Address Change
t
OH
(2) WRITE CYCLE
PARAMETER
SYMBOL
Write Cycle Time
t
WC
Address Valid to End of Write
t
AW
Chip Enable to End of Write
t
CW
Address Set-up Time
t
AS
Write Pulse Width
t
WP
Write Recovery Time
t
WR
Data to Write Time Overlap
t
DW
Data Hold from End of Write Time
t
DH
Output Active from End of Write
t
OW*
Write to Output in High Z
t
WHZ*
*These parameters are guaranteed by device characterization, but not production tested.
_____________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80027
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
8
10
UNIT
pF
pF
0V to 3.0V
5ns
1.5V
C
L
= 100pF, I
OH
/I
OL
= -1mA/4mA
UT62256C-35
MIN.
35
-
-
-
10
5
-
-
5
UT62256C-70
MIN.
70
-
-
-
10
5
-
-
5
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAX.
-
35
35
25
-
-
25
25
-
MAX.
-
70
70
35
-
-
35
35
-
UT62256C-35
MIN.
35
30
30
0
25
0
20
0
5
-
UT62256C-70
MIN.
70
60
60
0
50
0
30
0
5
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAX.
-
-
-
-
-
-
-
-
-
15
MAX.
-
-
-
-
-
-
-
-
-
25