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參數(shù)資料
| 型號(hào)： | UT621024LC-70LL |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 128K X 8 BIT LOW POWER CMOS SRAM |
| 中文描述： | 128K的× 8位低功耗CMOS SRAM |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 205K |
| 代理商： | UT621024LC-70LL |
UTRON
UT621024
Rev. 1.5
128K X 8 BIT LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled)
(1,2,4)
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
t
RC
Address
DOUT
Data Valid
t
AA
t
OH
t
OH
READ CYCLE 2 (
Notes :
1.
WE
is HIGH for read cycle.
2. Device is continuously selected
1
CE , CE2 and OE Controlled)
(1,3,5,6)
1
CE =V
IL
and CE2=V
IH.
3. Address must be valid prior to or coincident with
1
CE and CE2 transition; otherwise t
AA
is the limiting parameter.
4. OE is low.
5. t
CLZ1
, t
CLZ2
, t
OLZ
, t
CHZ1
, t
CHZ2
and t
OHZ
are specified with C
L
=5pF. Transition is measured
±
500mV from steady state.
6. At any given temperature and voltage condition, t
CHZ1
is less than t
CLZ1
, t
CHZ2
is less than t
CLZ2
, t
OHZ
is less than t
OLZ.
t
RC
t
AA
t
ACE1
t
ACE2
t
OE
t
OLZ
t
CLZ1
t
CLZ2
High-Z
t
CHZ1
t
CHZ2
t
OHZ
t
OH
Data Valid
High-Z
Address
1
CE
CE2
OE
D
OUT
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| UT621024LS-35L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
| UT621024LS-35LL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
| UT621024LS-55L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
| UT621024LS-55LL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
| UT621024LS-70L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
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