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參數(shù)資料
| 型號： | UT621024LC-35LL |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 128K X 8 BIT LOW POWER CMOS SRAM |
| 中文描述： | 128K的× 8位低功耗CMOS SRAM |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 205K |
| 代理商： | UT621024LC-35LL |
UTRON
UT621024
Rev. 1.5
128K X 8 BIT LOW POWER CMOS SRAM
WRITE CYCLE 1
(WE Controlled)
(1,2,3,5)
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
Address
D
OUT
High-Z
1
CE
WE
Data Valid
D
IN
CE2
t
CW2
t
CW1
t
AW
t
WC
t
WHZ
t
WP
t
AS
t
OW
t
DW
t
DH
t
WR
(4)
(4)
WRITE CYCLE 2
(
1
CE and CE2 Controlled)
(1,2,5)
Address
D
OUT
High-Z
1
CE
WE
(4)
Data Valid
D
IN
CE2
t
WC
t
AS
t
CW1
t
CW2
t
AW
t
WR
t
WP
t
WHZ
t
DW
t
DH
Notes :
1.
WE
or
1
CE must be HIGH or CE2 must be LOW during all address transitions.
2. A write occurs during the overlap of a low
1
CE , a high CE2 and a low
WE
.
3. During a
WE
controlled with write cycle with OE LOW, t
WP
must be greater than t
WHZ
+t
DW
to allow the I/O drivers
to turn off and data to be placed on the bus.
4. During this period, I/O pins are in the output state, and input singals must not be applied.
5. If the
1
CE LOW transition occurs simultaneously with or after
WE
LOW transition, the outputs remain in a high
impedance state.
6. t
OW
and t
WHZ
are specified with C
L
=5pF. Transition is measured
±
500mV from steady state.
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| UT621024LC-55LL | 128K X 8 BIT LOW POWER CMOS SRAM |
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|---|---|
| UT621024LC-55L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
| UT621024LC-55LL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
| UT621024LC-70L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
| UT621024LC-70LL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
| UT621024LS-35L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
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