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參數(shù)資料
| 型號(hào)： | UT621024 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 128K X 8 BIT LOW POWER CMOS SRAM |
| 中文描述： | 128K的× 8位低功耗CMOS SRAM |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 205K |
| 代理商： | UT621024 |
UTRON
UT621024
Rev. 1.5
128K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE
(T
A
=25
℃
, f=1.0MHz)
PARAMETER
SYMBOL
Input Capacitance
C
IN
Input/Output Capacitance
C
I/O
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5V
±
10% , T
A
= 0
℃
to 70
℃
)
(1) READ CYCLE
PARAMETER
SYMBOL
UT621024-35 UT621024-55 UT621024-70 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
t
RC
Address Access Time
t
AA
Chip Enable Access Time
t
ACE1
, t
ACE2
Output Enable Access Time
t
OE
Chip Enable to Output in Low-Z
t
CLZ1
*, t
CLZ2
*
Output Enable to Output in Low-Z t
OLZ
*
Chip Disable to Output in High-Z
t
CHZ1
*, t
CHZ2
*
Output Disable to Output in High-Z t
OHZ
*
Output Hold from Address Change t
OH
(2) WRITE CYCLE
PARAMETER
SYMBOL UT621024-
35
MIN.
Write Cycle Time
t
WC
Address Valid to End of Write
t
AW
Chip Enable to End of Write
t
CW1
, t
CW2
Address Set-up Time
t
AS
Write Pulse Width
t
WP
Write Recovery Time
t
WR
Data to Write Time Overlap
t
DW
Data Hold from End of Write-Time t
DH
Output Active from End of Write
t
OW
*
Write to Output in High-Z
t
WHZ
*
*These parameters are guaranteed by device characterization, but not production tested.
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
MIN.
-
-
MAX.
8
10
UNIT
pF
pF
0V to 3.0V
5ns
1.5V
C
L
=100pF, I
OH
/I
OL
=-1mA/4mA
35
-
-
-
10
5
-
-
5
-
55
-
-
-
10
5
-
-
5
-
70
-
-
-
10
5
-
-
5
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
35
25
-
-
25
25
-
55
55
30
-
-
30
30
-
70
70
35
-
-
35
35
-
UT621024-55 UT621024-70 UNIT
MAX. MIN. MAX. MIN. MAX.
-
55
-
-
50
-
-
50
-
-
0
-
-
40
-
-
0
-
-
25
-
-
0
-
-
5
-
15
-
20
35
30
30
0
25
0
20
0
5
-
70
60
60
0
45
0
30
0
5
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UT621024LC-35L | 128K X 8 BIT LOW POWER CMOS SRAM |
| UT621024LC-35LL | 128K X 8 BIT LOW POWER CMOS SRAM |
| UT621024LC-55L | 128K X 8 BIT LOW POWER CMOS SRAM |
| UT621024LC-55LL | 128K X 8 BIT LOW POWER CMOS SRAM |
| UT621024LC-70L | 128K X 8 BIT LOW POWER CMOS SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UT621024(E) | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:ASYNCHRONOUS STATIC RAM- High Speed |
| UT621024LC-35L | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
| UT621024LC-35LL | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
| UT621024LC-55L | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
| UT621024LC-55LL | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
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