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參數(shù)資料
| 型號： | UT621024(E) |
| 英文描述： | IC 2MEG FLSH(256KX16)BOTTOM SE |
| 中文描述： | 異步靜態(tài)RAM高速 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 109K |
| 代理商： | UT621024(E) |
UTRON
UT621024(E)
Rev. 1.1
128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80037
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
7
Notes :
1. WE , CE must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE , high CE2, low WE .
3. During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CE low transition and CE2 high transition occurs simultaneously with or after WE low transition, the outputs remain in a high
impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
DATA RETENTION CHARACTERISTICS (T
A = -20Jto +80J)
PARAMETER
SYMBOL TEST CONDITION
MIN.
TYP.
MAX.
UNIT
Vcc for Data Retention
VDR
CE VCC-0.2V or
CE2
≤ 0.2V
2.0
-
V
80
Data Retention Current
IDR
Vcc=3V
- L
-
1
20*
A
40
CE VCC-0.2V or
CE2
≤ 0.2V
- LL
-
0.5
10*
A
Chip Disable to Data
tCDR
See Data Retention
0
-
ns
Retention Time
Waveforms (below)
Recovery Time
tR
tRC*
-
ns
tRC* = Read Cycle Time
*Those parameters are for reference only under 50J
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) ( CE controlled)
VDR 2V
CE VCC-0.2V
Vcc(min.)
VIH
VCC
tR
tCDR
CE
Low Vcc Data Retention Waveform (2) (CE2 controlled)
VDR 2V
VCC(min.)
VCC
tR
tCDR
CE2 0.2V
VIL
CE2
VCC(min.)
VIL
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| UT621024LC-35L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
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| UT621024LC-55LL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
| UT621024LC-70L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
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