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參數(shù)資料
| 型號(hào)： | UT54LVDS032-UPXA |
| 廠商： | Aeroflex Inc. |
| 英文描述： | Quad Receiver |
| 中文描述： | 四接收機(jī) |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 78K |
| 代理商： | UT54LVDS032-UPXA |
6
AC SWITCHING CHARACTERISTICS
1, 2, 3, 4
(V
DD
= +5.0V + 10%, T
A
= -55
°
C to +125
°
C)
Notes:
1. Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the same chip with an event on the inputs.
2. Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z
0
= 50
, t
r
and t
f
(0% - 100%) < 1ns for R
IN
and t
r
and t
f
< 6ns for EN or EN.
3. C
L
includes probe and jig capacitance.
4. Guaranteed by characterization.
5. Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
SYMBOL
PARAMETER
MIN
MAX
UNIT
t
PHLD
Differential Propagation Delay High to Low
CL = 20pf (figures 4 and 5)
1.0
8.0
ns
t
PLHD
Differential Propagation Delay Low to High
CL = 20pf (figures 4 and 5)
1.0
8.0
ns
t
SKD
Differential Skew (t
PHLD
- t
PLHD
) (figures 4 and 5)
0
3.0
ns
t
SK1
4
Channel-to-Channel Skew
1
(figures 4 and 5)
0
3.0
ns
t
SK2
4
Chip-to-Chip Skew
5
(figures 4 and 5)
7.0
ns
t
TLH4
Rise Time (figures 4 and 5)
2.0
ns
t
THL
4
Fall Time (figures 4 and 5)
2.0
ns
t
PHZ
4
Disable Time High to Z (figures 6 and 7)
20
ns
t
PLZ
4
Disable Time Low to Z (figures 6 and 7)
20
ns
t
PZH4
Enable Time Z to High (figures 6 and 7)
20
ns
t
PZL
4
Enable Time Z to Low (figures 6 and 7)
20
ns
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