參數(shù)資料
型號(hào)： UT51C164MC-60
廠商： Electronic Theatre Controls, Inc.
英文描述： 256K X 16 BIT EDO DRAM
中文描述： 256 × 16位EDO公司的DRAM
文件頁(yè)數(shù)： 8/26頁(yè)
文件大?。?/td> 277K
代理商： UT51C164MC-60
UTRON
UT51C164
Rev 1.4
Notes:
1.
t
RCD
(Max.) is specified for reference only. Operation within
t
RCD
(Max.) limits insures that
t
RAC
(Max.) and
t
CAA
(Max.) can be met. If
t
RCD
is greater than the specified
t
RCD
(Max.), the access
time is controlled by
t
CAA
and
t
CAC.
2. Either
t
RRH
or
t
RCH
must be satisfied for Read Cycle to occur.
3. Measured with a load equivalent to one TTL input and 50pF.
4. Access time is determined by the longest of
t
CAA
,
t
CAC
and
t
CAP
.
5. Assumes that
t
RAD
≦
t
RAD
(Max.). If
t
RCD
is greater than
t
RCD
(Max.),
t
RAC
will increase by the
amount that
t
RCD
exceeds
t
RCD
(Max.)
6. Assumes that
t
RCD
≦
t
RCD
(Max.). If
t
RCD
is greater than
t
RCD
(Max.),
t
RAC
will increase by the
amount that
t
RAD
exceeds
t
RAD
(Max.)
7. Assumes that
t
RAD
≧
t
RAD
(Max.).
8. Operation within the
t
RAD
(Max.) limits ensures that
t
RA
can be met.
t
RAD
(Max.) is specified as a
reference point only. If
t
RAD
is greater than the specified
t
RAD
(Max.), the access time is controlled
by
t
CAA
and
t
CAC.
9.
t
WCS
,
t
RWD
,
t
AWD
and
t
CWD
are not restrictive operating parameters.
10.
t
WCS
(min.) must be satisfied in an Early Write Cycle.
11.
t
DS
and
t
DH
are referenced to the latter occurrence of CAS or
WE
.
12.
t
T
is measured between
V
IH
(min.) and
V
IL
(max.). AC-measurements assume
t
T
= 3ns.
13. Assumes a tri-state test load (5pF and a 500Ohm Thevenin equivalent).
14.An initial pause of 200us is required after power-up followed by any 8 CBR or ROR cycles
before device operation is achieved.
256K X 16 BIT EDO DRAM
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P90005
8
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