參數(shù)資料
型號: UT22VP10C-20UCX
英文描述: Fuse-Programmable PLD
中文描述: 保險絲,可編程的PLD
文件頁數(shù): 2/19頁
文件大小: 287K
代理商: UT22VP10C-20UCX
2
PRODUCT DESCRIPTION
The UT22VP10 RAD
PAL
is a fuse programmable logic array
device. The familiar sum-of-products (AND-OR) logic struc-
ture is complemented with a programmable macrocell. The
UT22VP10 is available in 24-pin DIP, 24-lead flatpack, and
28-lead quad-flatpack package offerings providing up to 22
inputs and 10 outputs. Amorphous silicon anti-fuse technology
provides the programming of each output. The user specifies
whether each of the potential outputs is registered or combina-
torial. Output polarity is also individually selected, allowing for
greater flexibility for output configuration. A unique output en-
able function allows the user to configure bidirectional I/O on
an individual basis.
The UT22VP10 architecture implements variable sum terms
providing 8 to 16 product terms to outputs. This feature provides
the user with increased logic function flexibility. Other features
include common synchronous preset and asynchronous reset.
These features eliminate the need for performing the initializa-
tion function.
The UT22VP10 provides a device with the flexibility to imple-
ment logic functions in the 500 to 800 gate complexity. The
flexible architecture supports the implementation of logic func-
tions requiring up to 21 inputs and only a single output or down
to 12 inputs and 10 outputs. Development and programming
support for the UT22VP10 is provided by DATA I/O.
DIP & FLATPACK PIN CONFIGURATION
QUAD-FLATPACK PIN CONFIGURATION
PIN NAMES
FUNCTION DESCRIPTION
The UT22VP10 RAD
PAL
implements logic functions as sum-
of-products expressions in a one-time programmable-AND/
fixed-OR logic array. User-defined functions are created by
programming the connections of input signals into the array.
User-configurable output structures in the form of I/O macro-
cells further increase logic flexibility.
CK/I
I
I
I
I
I
I
I
I
I
I
V
SS
V
DD
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CK/I
Clock/Data Input
I
Data Input
I/O
Data Input/Output
V
DD
Power
V
SS
Ground
5
6
7
8
9
11
10
12
13
14
15
16
17
18
24
23
22
21
20
19
25
1
2
3
4
28
27
26
I
I
I
V
SS
I
I
I
I/O2
I/O3
I/O4
V
SS
I/O5
I/O7
I/O6
V
DD
CK/I
I
I
V
DD
I/O0 I/O1
V
SS
I
I
I
I/O9 I/O8
V
SS
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