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參數(shù)資料
| 型號： | USB2SERA10CFK |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 7/28頁 |
| 文件大小： | 0K |
| 描述： | USB TO SERIAL BRIDGE |
| 標準包裝： | 490 |
| 特點： | USB 至 UART |
| 通道數(shù)： | 1，UART |
| FIFO's： | 512 字節(jié) |
| 規(guī)程： | RS232，RS485，USB 2.0 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 帶自動流量控制功能： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VQFN 裸露焊盤 |
| 供應商設備封裝： | 24-QFN 裸露焊盤（5x5） |
| 包裝： | 托盤 |
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Electrical Characteristics
USB2SERA10 Data Sheet, Rev. 2
Freescale Semiconductor
15
3. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and can result
in the external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if the clock rate is very low which reduces overall power consumption.
A.3
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic. It is user-determined rather than
being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual
pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current
(heavy loads), the difference between pin voltage and VSS or VDD will be very small.
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance
2. Junction to Ambient Natural Convection
3. 1s — Single layer board, one signal layer
4. 2s2p — Four layer board, 2 signal and 2 power layers
The average chip-junction temperature (TJ) in × ° C can be obtained from:
Eqn. 1
Where:
TA — Ambient temperature,° C
JA — Package thermal resistance, junction-to-ambient,° C/W
PD — Pint + PI/OPint = IDD × VDD, Watts — chip internal power
PI/O — Power dissipation on input and output pins — user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected)
is:
Eqn. 2
Table A-3. Absolute maximum ratings
Rating
Symbol
Value
Unit
Operating temperature range (packaged)
T
A
T
L to TH
-40 to 85
° C
Thermal Resistance 1, 2, 3, 4
24-pin QFN
1s
2s2p
JA
92
33
° C/W
T
j
T
A
P
D
Iq
JA
P
D
JA
+
=
PD
K
T
J
273
C
+
=
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