參數(shù)資料
型號: USB1T11A
廠商: Fairchild Semiconductor Corporation
英文描述: Universal Serial Bus Transceiver
中文描述: 通用串行總線收發(fā)器
文件頁數(shù): 5/11頁
文件大小: 558K
代理商: USB1T11A
5
www.fairchildsemi.com
U
DC Electrical Characteristics
(D /D Pins)
Over recommended range of supply voltage and operating free air temperature (unless otherwise noted). V
CC
3.0V to 3.6V
Note 5:
Excludes external resistor. In order to comply with USB Specification 1.1, external series resistors of 24
:
r
1% each on D and D are recom-
mended. This specification is guaranteed by design and statistical process distribution.
Note 6:
This specification is guaranteed by design and statistical process distribution.
AC Electrical Characteristics
(D /D Pins, Full Speed)
Over recommended range of supply voltage and operating free air temperature (unless otherwise noted). V
CC
3.0V to 3.6V
C
L
50 pF; R
L
1.5 k
:
on D to V
CC
Symbol
Parameter
Test Conditions
Limits
Units
Temp
40
q
C to 85
q
C
Min
Typ
Max
INPUT LEVELS:
V
DI
V
CM
V
SE
Differential Input Sensitivity
Differential Common Mode Range
Single Ended Receiver Threshold
|(D )
(D )|
Includes V
DI
Range
0.2
0.8
0.8
V
V
V
2.5
2.0
OUTPUT LEVELS:
Static Output LOW Voltage
Static Output HIGH Voltage
V
OL
V
OH
V
CR
R
L
of 1.5 k
:
to 3.6V
R
L
of 15 k
:
to GND
0.3
3.6
V
V
2.8
Differential Crossover
LEAKAGE CURRENT:
High Z State Data Line Leakage Current 0V V
IN
3.3V
CAPACITANCE:
Transceiver Capacitance
Capacitance Match
1.3
2.0
V
I
OZ
r
5
P
A
C
IN
(Note 6)
Pin to GND
10
10
pF
%
OUTPUT RESISTANCE:
Z
DRV
(Note 5) Driver Output Resistance
Resistance Match
Steady State Drive
4
20
10
:
%
Symbol
Parameter
Test Condition
Limits
Units
Temp
40
q
C to 85
q
C
Min
Typ
Max
DRIVER CHARACTERISTICS:
10% and 90%
Figure 1
ns
t
R
t
F
t
RFM
V
CRS
Rise Time
4
20
Fall Time
Rise/Fall Time Matching
Output Signal Crossover Voltage
Figure 1
(t
r
/t
f
)
4
90
1.3
20
110
2.0
%
V
DRIVER TIMINGS:
Driver Propagation Delay
(VPO, VMO/FSEO to D /D )
t
PLH
t
PLH
t
PHZ
Figure 2
Figure 2
18
18
ns
ns
Driver Disable Delay
Figure 4
13
ns
t
PLZ
t
PZH
(OE to D /D )
Driver Enable Delay
Figure 4
Figure 4
13
17
ns
ns
t
PZL
(OE to D /D )
RECEIVER TIMINGS:
Figure 4
17
ns
t
PLH
t
PHL
t
PLH
t
PHL
Receiver Propagation Delay
(D , D to RCV)
Single-ended Receiver Delay
Figure 3
Figure 3
Figure 3
16
19
8
ns
ns
ns
(D , D to VP, VM)
Figure 3
8
ns
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