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參數(shù)資料
| 型號： | US2075 |
| 廠商： | Unisem Group |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 42K |
| 代理商： | US2075 |
US2075
4-3
Rev. 1.2
4/26/98
PIN DESCRIPTIONS
PIN # PIN SYMBOL
3
PIN DESCRIPTION
A resistor divider from this pin to the output of the switching regulator and
ground sets the core supply voltage.
The output of the linear regulator. A minimum of a 10uF capacitor must be
connected from this pin to ground to insure stability. This voltage is set at 3.30V typ.
The input pin of the regulator. Typically a large storage capacitor is connected from
this pin to ground to insure that the input voltage does not sag below the minimum
drop out voltage during the load transient response. This pin must always be 1.3V
higher than Vout in order for the device to regulate properly.
This pin is connected to the IC substrate and must be connected to the lowest
potential in the system. It is also connected to the Tab of the package. A high
frequency capacitor must be connected from V12 to this pin to insure proper operation.
The PWM output of the switching controller. This pin is a totem pole drive that is
connected to the gate of the power MOSFET. A resistor may be placed from this
pin to the gate in order to reduce switching noise.
A resistor is connected from this pin to the Vfb pin to set the output ripple voltage.
See application note for more details.
This pin is connected to the 12V supply voltage A high frequency cap must be
connected from this pin to the GND pin of the IC.
Vfb
6
Vout
7
V5
4
Gnd
1
Drv
5
Vhyst
2
V12
BLOCK DIAGRAM
Figure 1 - Simplified block diagram of the US2075
Note 1 :
Low duty cycle pulse testing with Kelvin con-
nections are required in order to maintain accurate data.
Vref
7.5A LDO
UVLO
1.25V
PWM Control
V12
2
Vhyst
5
V5
7
Drv
1
Gnd
4
Vfb
3
Vout
6
2075blk1-1.0
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