參數(shù)資料
型號(hào): US1881
英文描述: US1881 General Purpose Hall effect Latch
中文描述: US1881通用霍爾效應(yīng)鎖存
文件頁(yè)數(shù): 7/9頁(yè)
文件大?。?/td> 162K
代理商: US1881
3901001881
Rev. 012
Page 7
Aug/02
Physical Characteristics
U18
805
1
2
3
*
All Dimensions in millimeters
2.13
1.87
0.45
0.41
Marked
Surface
1.53
UA Hall Plate / Chip Location
1.60
45
o
Typical
4.30
3.90
2.64
0.84
3.20
1.75
0.48
0.43
0.20
0.41
1.30
1.24
2.57
o
Ty5
0.38
(sTypical
15.0
0.41
0.35
UA Package Dimensions
* MARKING:
Line 1:
1st digit (U)
2nd and 3rd digits (18)
= Supplier (Melexis)
= Series (1880)
Line 2:
1st digit (8)
2nd and 3rd digits(05)
= Year (1998)
= Week of Year
PINOUT:
Pin 1
Pin 2
Pin 3
V
GND
Output
NOTES:
1.) Controlling dimension: mm
2.) Leads must be free of flash and
plating voids
3.) Do not bend leads within 1mm of
the lead to package interface.
4.) Package dimensions exclude
molding flash
5.) Tolerance is 0.254mm unless
otherwise specified
SOT-23 Hall Plate /
Chip Location
(Bottom View)
SOT-23 Package Dimensions
(Top View)
NOTES:
1. MARKING:
1st Digit (1) = Series (1880)
2nd Digit(6) = Year - 1996
Last Digits (51) = Week of Year
2. PINOUT (See Top View at left):
Pin 1
VDD
Pin 2
Output
Pin 3
GND
3. Controlling dimension: mm.
4. Lead thickness after solder plating will be 0.254
mm maximum.
5. Package dimensions exclude molding flash.
6. The end flash shall not exceed 0.127 mm on each
side of package.
7. Tolerance is +/- 0.254 mm unless otherwise
specified.
1.55
0.95
1651
1.30
1.00
0.10
3.10
3.00
2.60
0.50
0.35
1.80
1.50
chip
0.20
MIN
0.25
0.10
2.10
1.70
0.90
0.70
*
1
2
3
Pin #
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