參數(shù)資料
型號(hào): UPSD3432E-40T6T
廠商: 意法半導(dǎo)體
英文描述: Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic
中文描述: Turbo Plus系列高速渦輪8032 USB和可編程邏輯控制器
文件頁(yè)數(shù): 199/264頁(yè)
文件大?。?/td> 4320K
代理商: UPSD3432E-40T6T
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uPSD34xx - PSD MODULE
I/O Ports.
There are four programmable I/O ports
on the PSD Module: Port A (80-pin device only),
Port B, Port C, and Port D. Ports A and B are eight
bits each, Port C is four bits, and Port D is two bits
for 80-pin devices or 1-bit for 52-pin devices. Each
port pin is individually configurable, thus allowing
multiple functions per port. The ports are config-
ured using PSDsoft Express then programming
with JTAG, and also by the 8032 writing to csiop
registers at run-time.
Topics discussed in this section are:
General Port architecture
Port Operating Modes
Individual Port Structure
General Port Architecture.
The general archi-
tecture for a single I/O Port pin is shown in
Figure
80., page 200
. Port structures for Ports A, B, C,
and D differ slightly and are shown in
Figure
85., page 212
though
Figure 88., page 217
.
Figure 80., page 200
shows four csiop registers
whose outputs are determined by the value that
the 8032 writes to csiop Direction, Drive, Control,
and Data Out. The I/O Port logic contains an out-
put mux whose mux select signal is determined by
PSDsoft Express and the csiop Control register
bits at run-time. Inputs to this output mux include
the following:
1.
Data from the csiop Data Out register for MCU
I/O output mode (All ports)
2.
Latched de-multiplexed 8032 Address for
Address Output mode (Ports A and B only)
3.
Peripheral I/O mode data bit (Port A only)
4.
GPLD OMC output (Ports A, B, and C).
The Port Data Buffer (PDB) provides feedback to
the 8032 and allows only one source at a time to
be read when the 8032 reads various csiop regis-
ters. There is one PDB for each port pin enabling
the 8032 to read the following on a pin-by-pin ba-
sis:
1.
MCU I/O signal direction setting (csiop
Direction reg)
2.
Pin drive type setting (csiop Drive Select reg)
3.
Latched Addr Out mode setting (csiop Control
reg)
4.
MCU I/O pin output setting (csiop Data Out
reg)
5.
Output Enable of pin driver (csiop Enable Out
reg)
6.
MCU I/O pin input (csiop Data In reg)
A port pin’s output enable signal is controlled by a
two input OR gate whose inputs come from: a
product term of the AND-OR array; the output of
the csiop Direction Register. If an output enable
from the AND-OR Array is not defined, and the
port pin is not defined as an OMC output, and if
Peripheral I/O mode is not used, then the csiop Di-
rection Register has sole control of the OE signal.
As shown in
Figure 80., page 200
, a physical port
pin is connected to the I/O Port logic and is also
separately routed to an IMC, allowing the 8032 to
read a port pin by two different methods (MCU I/O
input mode or read the IMC).
Port Operating Modes.
I/O Port logic has sever-
al modes of operation.
Table 115., page 197
sum-
marizes which modes are available on each port.
Each of the port operating modes are described in
following sections. Some operating modes can be
defined using PSDsoft Express, and some by the
8032 writing to the csiop registers at run-time, and
some require both. For example, PLD I/O, Latched
Address Out, and Peripheral I/O modes must be
defined in PSDsoft Express and programmed into
the device using JTAG, but an additional step
must happen at run-time to activate Latched Ad-
dress Out mode and Peripheral I/O mode, but not
needed for PLD I/O. In another example, MCU I/O
mode is controlled completely by the 8032 at run-
time and only a simple pin name declaration is
needed in PSDsoft Express for documentation.
Table 116., page 197
summarizes what actions
are needed in PSDsoft Express and what actions
are required by the 8032 at run-time to achieve the
various port functions.
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