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參數(shù)資料
| 型號： | UPSD3424E |
| 廠商： | 意法半導體 |
| 英文描述： | High Speed CMOS Logic Non-Inverting Octal Buffer/Line Drivers with 3-State Outputs 20-SOIC -55 to 125 |
| 中文描述： | Turbo Plus系列高速渦輪8032 USB和可編程邏輯控制器 |
| 文件頁數(shù)： | 50/264頁 |
| 文件大小： | 4320K |
| 代理商： | UPSD3424E |
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uPSD34xx - POWER SAVING MODES
50/264
POWER SAVING MODES
The uPSD34xx is a combination of two die, or
modules, each module having its own current con-
sumption characteristics. This section describes
reduced power modes for the MCU Module. See
the section,
Power Management, page 168
for re-
duced power modes of the PSD Module. Total cur-
rent consumption for the combined modules is
determined in the DC specifications at the end of
this document.
The MCU Module has three software-selectable
modes of reduced power operation.
Idle Mode
Power-down Mode
Reduced Frequency Mode
Idle Mode
Idle Mode will halt the 8032 MCU core while leav-
ing the MCU peripherals active (Idle Mode blocks
MCU_CLK only). For lowest current consumption
in this mode, it is recommended to disable all un-
used peripherals, before entering Idle mode (such
as the ADC and the Debug Unit breakpoint com-
parators). The following functions remain fully ac-
tive during Idle Mode (except if disabled by SFR
settings).
External Interrupts INT0 and INT1
Timer 0, Timer 1 and Timer 2
Supervisor reset from: LVD, JTAG Debug,
External RESET_IN_, but
not
the WTD
ADC
I
2
C Interface
UART0 and UART1 Interfaces
SPI Interface
Programmable Counter Array
USB Interface
An interrupt generated by any of these peripher-
als, or a reset generated from the supervisor, will
cause Idle Mode to exit and the 8032 MCU will re-
sume normal operation.
The output state on I/O pins of MCU ports 1, 3, and
4 remain unchanged during Idle Mode.
To enter Idle Mode, the 8032 MCU executes an in-
struction to set the IDL bit in the SFR named
PCON, shown in
Table 26., page 52
. This is the
last instruction executed in normal operating mode
before Idle Mode is activated. Once in Idle Mode,
the MCU status is entirely preserved, and there
are no changes to: SP, PSW, PC, ACC, SFRs,
DATA, IDATA, or XDATA.
The following are factors related to Idle Mode exit:
–
Activation of any enabled interrupt will cause
the IDL bit to be cleared by hardware,
terminating Idle Mode. The interrupt is
■
■
■
■
■
■
■
■
■
■
■
■
serviced, and following the Return from
Interrupt instruction (RETI), the next
instruction to be executed will be the one
which follows the instruction that set the IDL
bit in the PCON SFR.
After a reset from the supervisor, the IDL bit is
cleared, Idle Mode is terminated, and the MCU
restarts after three MCU machine cycles.
Power-down Mode
Power-down Mode will halt the 8032 core and all
MCU peripherals (Power-down Mode blocks
MCU_CLK, USB_CLK, and PERIPH_CLK). This
is the lowest power state for the MCU Module.
When the PSD Module is also placed in Power-
down mode, the lowest total current consumption
for the combined die is achieved for the
uPSD34xx. See
Power Management, page 168
in
the PSD Module section for details on how to also
place the PSD Module in Power-down mode. The
sequence of 8032 instructions is important when
placing both modules into Power-down Mode.
The instruction that sets the PD Bit in the SFR
named PCON (
Table 26., page 52
) is the last in-
struction executed prior to the MCU Module going
into Power-down Mode. Once in Power-down
Mode, the on-chip oscillator circuitry and all clocks
are
stopped.
The
SFRs,
and XDATA are preserved.
Power-down Mode is terminated only by a reset
from the supervisor, originating from the
RESET_IN_ pin, the Low-Voltage Detect circuit
(LVD), or a JTAG Debug reset command. Since
the clock to the WTD is not active during Power-
down mode, it is not possible for the supervisor to
generate a WDT reset.
Table 24., page 51
summarizes the status of I/O
pins and peripherals during Idle and Power-down
Modes on the MCU Module.
Table 25., page 51
shows the state of 8032 MCU address, data, and
control signals during these modes.
Reduced Frequency Mode
The 8032 MCU consumes less current when oper-
ating at a lower clock frequency. The MCU can re-
duce its own clock frequency at run-time by writing
to three bits, CPUPS[2:0], in the SFR named
CCON0 described in
Table 22., page 49
. These
bits effectively divide the clock frequency (f
OSC
)
coming in from the external crystal or oscillator de-
vice. The clock division range is from 1/2 to 1/
2048, and the resulting frequency is f
MCU
.
This MCU clock division does not affect any of the
peripherals, except for the WTD. The clock driving
the WTD is the same clock driving the 8032 MCU
core as shown in
Figure 14., page 48
.
–
DATA,
IDATA,
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| UPSD3433E-40T6 | 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| UPSD3433E-40U6 | 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| UPSD3433EB40T6 | 功能描述:8位微控制器 -MCU Turbo 8032 MCU w/USB & Programmable Logic RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| UPSD3433EB40U6 | 功能描述:8位微控制器 -MCU uPSD34x Turbo Plus Fast Turbo 8032 MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| UPSD3433EV-40T6 | 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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