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參數(shù)資料
| 型號(hào)： | UPSD3423E |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | High Speed CMOS Logic Non-Inverting Octal Buffer/Line Drivers with 3-State Outputs 20-SOIC -55 to 125 |
| 中文描述： | Turbo Plus系列高速渦輪8032 USB和可編程邏輯控制器 |
| 文件頁(yè)數(shù)： | 184/264頁(yè) |
| 文件大?。?/td> | 4320K |
| 代理商： | UPSD3423E |
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uPSD34xx - PSD MODULE
184/264
Ready/Busy (PC3).
This signal can be used to
output the Ready/Busy status of a program or
erase operation on either Flash memory. The out-
put on the Ready/Busy pin is a ’0’ (Busy) when ei-
ther Flash memory array is being written,
or
when
either Flash memory array is being erased. The
output is a ’1’ (Ready) when no program or erase
operation is in progress. To activate this function
on this pin, the user must select the “Ready/Busy”
selection in PSDsoft Express when configuring pin
PC3. This pin may be polled by the 8032 or used
as a 8032 interrupt to indicate when an erase or
program operation is complete (requires routing
the signal on PC board from PC3 back into a pin
on the MCU Module). This signal is also available
internally on the PSD Module as an input to both
PLDs (without routing a signal externally on PC
board) and its signal name is “rd_bsy”. The Ready/
Busy output can be probed during lab develop-
ment to check the timing of Flash memory pro-
gramming in the system at run-time.
Bypassed Unlock Sequence.
The Bypass Un-
lock mode allows the 8032 to program bytes in the
Flash memories faster than using the standard
Flash program instruction sequences because the
typical AAh, 55h unlock bus cycles are bypassed
for each byte that is programmed. Bypassing the
unlock sequence is typically used when the 8032
is intentionally programming a large number of
bytes (such as during IAP). After intentional pro-
gramming is complete, typically the Bypass mode
would be disabled, and full protection is back in
place to prevent unwanted WRITEs to Flash mem-
ory.
The Bypass Unlock mode is entered by first initiat-
ing two Unlock bus cycles. This is followed by a
third WRITE operation containing the Bypass Un-
lock command, 20h (as shown in
Table
107., page 179
). The Flash memory array that re-
ceived that sequence then enters the Bypass Un-
lock mode. After this, a two bus cycle program
operation is all that is required to program a byte
in this mode. The first bus cycle in this shortened
program instruction sequence contains the By-
passed Unlocked Program command, A0h, to any
valid address within the unlocked Flash array. The
second bus cycle contains the address and data of
the byte to be programmed. Programming status
is checked using toggle, polling, or Ready/Busy
just as before. Additional data bytes are pro-
grammed the same way until this Bypass Unlock
mode is exited.
To exit Bypass Unlock mode, the system must is-
sue the Reset Bypass Unlock instruction se-
quence. The first bus cycle of this instruction must
write 90h to any valid address within the unlocked
Flash Array; the second bus cycle must write 00h
to any valid address within the unlocked Flash Ar-
ray. After this sequence the Flash returns to Read
Array mode.
During Bypass Unlock Mode, only the Bypassed
Unlock Program instruction, or the Reset Bypass
Unlock instruction is valid, other instruction will be
ignored.
Erasing Flash Memory.
Flash memory may be
erased sector-by-sector, or an entire Flash memo-
ry array may be erased with one command (bulk).
Flash Bulk Erase.
The Flash Bulk Erase instruc-
tion sequence uses six WRITE operations fol-
lowed by a READ operation of the status register,
as described in
Table 107., page 179
. If any byte
of the Bulk Erase instruction sequence is wrong,
the Bulk Erase instruction sequence aborts and
the device is reset to the Read Array mode. The
address provided by the 8032 during the Flash
Bulk Erase command sequence may select any
one of the eight Flash memory sector select sig-
nals FSx or one of the four signals CSBOOTx. An
erase of the entire Flash memory array will occur
in a particular array even though a command was
sent to just one of the individual Flash memory
sectors within that array.
During a Bulk Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5), the
Toggle Flag Bit (DQ6), and the Data Polling Flag
Bit (DQ7). The Error Flag Bit (DQ5) returns a ’1’ if
there has been an erase failure. Details of acquir-
ing the status of the Bulk Erase operation are de-
tailed in the section entitled “
Programming Flash
Memory., page 181
.
During a Bulk Erase operation, the Flash memory
does not accept any other Flash instruction se-
quences.
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| UPSD3433E-40T6 | 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| UPSD3433E-40U6 | 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| UPSD3433EB40T6 | 功能描述:8位微控制器 -MCU Turbo 8032 MCU w/USB & Programmable Logic RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| UPSD3433EB40U6 | 功能描述:8位微控制器 -MCU uPSD34x Turbo Plus Fast Turbo 8032 MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| UPSD3433EV-40T6 | 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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