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參數(shù)資料
| 型號(hào)： | UPSD3352D-40U6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Turbo Series Fast 8032 MCU with Programmable Logic |
| 中文描述： | Turbo系列8032微控制器的快速可編程邏輯 |
| 文件頁(yè)數(shù)： | 187/231頁(yè) |
| 文件大?。?/td> | 3722K |
| 代理商： | UPSD3352D-40U6T |
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uPSD33xx
Power Management.
The PSD Module offers
configurable power saving options, and also a way
to manage power to the SRAM (battery backup).
These options may be used individually or in com-
binations. A top level description for these func-
tions is given here, then more detailed
descriptions will follow.
–
Zero-Power Memory:
All memory arrays
(Flash and SRAM) in the PSD Module are built
with zero-power technology, which puts the
memories into standby mode (~ zero DC
current) when 8032 address signals are not
changing. As soon as a transition occurs on
any address input, the affected memory
“wakes up”, changes and latches its outputs,
then goes back to standby. The designer does
not have to do anything special to achieve this
memory standby mode when no inputs are
changing—it happens automatically. Thus,
the slower the 8032 clock, the lower the
current consumption.
Both PLDs (DPLD and GPLD) are also zero-
power, but this is not the default condition. The
8032 must set a bit in one of the csiop PMMR
registers at run-time to achieve zero-power.
–
Automatic Power-Down (APD):
The APD
feature allows the PSD Module to reach it’s
lowest current consumption levels. If enabled,
the APD counter will time-out when there is a
lack of 8032 bus activity for an extended
amount of time (8032 asleep). After time-out
occurs, all 8032 address and data buffers on
the PSD Module are shut down, preventing
the PSD Module memories and potentially the
PLDs from waking up from standby, even if
address inputs are changing state because of
noise or any external components driving the
address lines. Since the actual address and
data buffers are turned off, current
consumption is even further reduced.
Note:
Non-address signals are still available
to PLD inputs and will wake up the PLDs if
these signals are changing state, but will not
wake up the memories.
The APD counter requires a relatively slow
external clock input on pin PD1 that does stop
when the 8032 goes to sleep mode.
–
Forced Power-Down (FPD):
The MCU can
put the PSD Module into Power-Down mode
with the same results as using APD described
above, but FPD does not rely on the APD
counter. Instead, FPD will force the PSD
Module into Power-Down mode when the
MCU firmware sets a bit in one of the csiop
PMMR registers. This is a good alternative to
APD because no external clock is needed for
the APD counter.
–
PSD Module Chip Select Input (CSI):
This
input on pin PD2 (80-pin devices only) can be
used to disable the internal memories, placing
them in standby mode even if address inputs
are changing. This feature does not block any
internal signals (the address and data buffers
are still on but signals are ignored) and CSI
does not disable the PLDs. This is a good
alternative to using the APD counter, which
requires an external clock on pin PD1.
Non-Turbo Mode:
The PLDs can operate in
Turbo or non-Turbo modes. Turbo mode has
the shortest signal propagation delay, but
consumes more current than non-Turbo
mode. A csiop register can be written by the
8032 to select modes, the default mode is with
Turbo mode enabled. In non-Turbo mode, the
PLDs can achieve very low standby current (~
zero DC current) while no PLD inputs are
changing, and the PLDs will even use less AC
current when inputs do change compared to
Turbo mode.
When the Turbo mode is enabled, there is a
significant DC current component AND the AC
current component is higher than non-Turbo
mode, as shown in
Figure 85., page 202
(5V)
and
Figure 86., page 202
(3.3V).
Blocking Bits:
Significant power savings can
be achieved by blocking 8032 bus control
signals (RD, WR, PSEN, ALE) from reaching
PLD inputs, if these signals are not used in
any PLD equations. Blocking is achieved by
the 8032 writing to the “blocking bits” in csiop
PMMR registers. Current consumption of the
PLDs is directly related to the composite
frequency of all transitions on PLD inputs, so
blocking certain PLD inputs can significantly
lower PLD operating frequency and power
consumption (resulting in a lower frequency
on the graphs of
Figure 85., page 202
and
Figure 86., page 202
).
SRAM Backup Voltage:
Pin PC2 can be
configured in PSDsoft to accept an alternate
DC voltage source (battery) to automatically
retain the contents of SRAM when V
DD
drops
below this alternate voltage.
Note:
It is recommended to prevent unused
inputs from floating on Ports A, B, C, and D by
pulling them up to V
DD
with a weak external
resistor (100K
), or by setting the csiop
Direction register to “output” at run-time for all
unused inputs. This will prevent the CMOS
input buffers of unused input pins from
drawing excessive current.
The csiop PMMR register definitions are shown in
117
through
Table 119., page 188
.
–
–
–
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPSD3352DV-40T6T | Turbo Series Fast 8032 MCU with Programmable Logic |
| UPSD3352DV-40U6T | Turbo Series Fast 8032 MCU with Programmable Logic |
| UPSD3353DV-40T6T | Turbo Series Fast 8032 MCU with Programmable Logic |
| UPSD3353DV-40U6T | Turbo Series Fast 8032 MCU with Programmable Logic |
| UPSD3354DV-40T6T | Turbo Series Fast 8032 MCU with Programmable Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| UPSD3354D-40T6 | 功能描述:8位微控制器 -MCU 8032 MCU USB RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| UPSD3354D-40U6 | 功能描述:8位微控制器 -MCU 8BIT Fast 8032 MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| UPSD3354DV-40T6 | 功能描述:8位微控制器 -MCU 8032 MCU USB RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| UPSD3354DV-40U6 | 功能描述:8位微控制器 -MCU FAST 8032 8BIT MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| UPSD3422E-40T6 | 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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