參數(shù)資料
型號： UPSD3254BV-40U1
廠商： 意法半導(dǎo)體
英文描述： Two and Three Channel Codewheels
中文描述： 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核
文件頁數(shù)： 31/176頁
文件大?。?/td> 1214K
代理商： UPSD3254BV-40U1
31/176
μPSD325X DEVICES
μPSD325X HARDWARE DESCRIPTION
The
μPSD325X devices have a modular architec-
ture with two main functional modules: the MCU
Module and the PSD Module. The MCU Module
consists of a standard 8032 core, peripherals and
other system supporting functions. The PSD Mod-
ule provides configurable Program and Data mem-
ories to the 8032 CPU core. In addition, it has its
own set of I/O ports and a PLD with 16 macrocells
for general logic implementation. Ports A,B,C, and
D are general purpose programmable I/O ports
that have a port architecture which is different from
Ports 0-4 in the MCU Module.
The PSD Module communicates with the CPU
Core through the internal address, data bus (A0-
A15, D0-D7) and control signals (RD_, WR_,
PSEN_ , ALE, RESET_). The user defines the De-
coding PLD in the PSDsoft Development Tool and
can map the resources in the PSD Module to any
program or data address space.
Figure 15. μPSD325X devices Functional Modules
AI07802
4
Channel
ADC
1Mb or 2Mb
Main Flash
Decode PLD
256Kb
SRAM
CPLD - 16 MACROCELLS
JTAG ISP
Port 1
Port 3
2 UARTs
Interrupt
3 Timer /
Counters
256 Byte SRAM
8032 Core
Port 3, UART,
Intr, Timers,I2C
PSD Internal Bus
8032 Internal Bus
USB
&
Transceiver
Port 1, Timers and
2nd UART and ADC
DDC
w/ 256 Byte
SRAM
PWM
5
Channels
Port 4 PWM
and DDC
Dedicated
USB Pins
Port A & B, PLD
I/O and GPIO
Port D
GPIO
Port C,
JTAG, PLD I/O
and GPIO
VCC, GND,
XTAL
256Kb
Secondary
Flash
Dedicated
Pins
I2C
Port 0, 2
Ext. Bus
Reset Logic
LVD & WDT
Bus
Interface
Reset
D0-D7
A0-A15
RD,PSEN
WR,ALE
Page Register
PSD MODULE
MCU MODULE
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