參數資料
型號: uPSD3254BV-24U1T
廠商: 意法半導體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core
中文描述: 閃存可編程系統(tǒng)設備與8032微控制器內核
文件頁數: 138/175頁
文件大小: 1731K
代理商: UPSD3254BV-24U1T
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
138/175
Table 102. Power Management Mode Registers PMMR2
Note: The bits of this register are cleared to zero following Power-up. Subsequent RESET pulses do not clear the registers.
Table 103. APD Counter Operation
Bit 0
X
0
Not used, and should be set to zero.
Bit 1
X
0
Not used, and should be set to zero.
Bit 2
PLD Array
WR
0 = on WR input to the PLD AND Array is connected.
1 = off WR input to PLD AND Array is disconnected, saving power.
Bit 3
PLD Array
RD
0 = on RD input to the PLD AND Array is connected.
1 = off RD input to PLD AND Array is disconnected, saving power.
Bit 4
PLD Array
PSEN
0 = on PSEN input to the PLD AND Array is connected.
1 = off PSEN input to PLD AND Array is disconnected, saving power.
Bit 5
PLD Array
ALE
0 = on ALE input to the PLD AND Array is connected.
1 = off ALE input to PLD AND Array is disconnected, saving power.
Bit 6
X
0
Not used, and should be set to zero.
Bit 7
X
0
Not used, and should be set to zero.
APD Enable Bit
ALE Level
APD Counter
0
X
Not Counting
1
Pulsing
Not Counting
1
0 or 1
Counting (Generates PDN after 15 Clocks)
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相關代理商/技術參數
參數描述
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