參數(shù)資料
型號： UPSD3254B-40U1
廠商： 意法半導(dǎo)體
元件分類： 8位微控制器
英文描述： 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash
中文描述： 8位微控制器與2/4/8K字節(jié)在系統(tǒng)可編程閃存
文件頁數(shù)： 141/176頁
文件大小： 1214K
代理商： UPSD3254B-40U1
141/176
μPSD325X DEVICES
Table 105. Status During Power-on RESET, Warm RESET and Power-down Mode
Note: 1. The SR_cod and PeriphMode Bits in the VM Register are always cleared to ’0’ on Power-on RESET or Warm RESET.
Port Configuration
Power-On RESET
Warm RESET
Power-down Mode
MCU I/O
Input mode
Input mode
Unchanged
PLD Output
Valid after internal PSD
configuration bits are
loaded
Valid
Depends on inputs to PLD
(addresses are blocked in
PD Mode)
Address Out
Tri-stated
Tri-stated
Not defined
Peripheral I/O
Tri-stated
Tri-stated
Tri-stated
Register
Power-On RESET
Warm RESET
Power-down Mode
PMMR0 and PMMR2
Cleared to ’0’
Unchanged
Unchanged
Macrocells flip-flop status
Cleared to ’0’ by internal
Power-on RESET
Depends on .re and .pr
equations
Depends on .re and .pr
equations
VM Register
1
Initialized, based on the
selection in PSDsoft
Configuration menu
Initialized, based on the
selection in PSDsoft
Configuration menu
Unchanged
All other registers
Cleared to ’0’
Cleared to ’0’
Unchanged
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