參數(shù)資料
型號: uPSD3253AV-24T1T
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core
中文描述: 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核
文件頁數(shù): 128/175頁
文件大?。?/td> 1731K
代理商: UPSD3253AV-24T1T
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
128/175
Figure 64. Peripheral I/O Mode
Table 91. Port Operating Modes
Note: 1. Port A is not available in the 52-pin package.
2. On pins PC2, PC3, PC4, and PC7 only.
3. JTAG pins (TMS, TCK, TDI, TDO) are dedicated pins.
Table 92. Port Operating Mode Settings
Note: 1. N/A = Not Applicable
2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product
term (.oe) from the CPLD AND Array.
Table 93. I/O Port Latched Address Output Assignments
Port Mode
Port A
(1)
Port B
Port C
Port D
MCU I/O
Yes
Yes
Yes
Yes
PLD I/O
McellAB Outputs
McellBC Outputs
Additional Ext. CS Outputs
PLD Inputs
Yes
No
No
Yes
Yes
Yes
No
Yes
No
Yes
(2)
No
Yes
No
No
Yes
Yes
Address Out
Yes (A7 – 0)
Yes (A7 – 0)
No
No
Peripheral I/O
Yes
No
No
No
JTAG ISP
No
No
Yes
(3)
No
Mode
Defined in PSDsoft
Control Register
Setting
(1)
Direction Register
Setting
(1)
VM Register Setting
(1)
MCU I/O
Declare pins only
0
1 = output,
0 = input (Note 2)
N/A
PLD I/O
Logic equations
N/A
(Note
2)
N/A
Address Out
(Port A,B)
Declare pins only
1
1 (Note
2)
N/A
Peripheral I/O
(Port A)
Logic equations
(PSEL0 & 1)
N/A
N/A
PIO Bit = 1
Port A (PA3-PA0)
Port A (PA7-PA4)
Port B (PB3-PB0)
Port B (PB7-PB4)
Address a3-a0
Address a7-a4
Address a3-a0
Address a7-a4
RD
PSEL0
PSEL1
PSEL
VM REGISTER BIT 7
WR
PA0-PA7
D0-D7
DATA BUS
AI02886
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