參數(shù)資料
型號: uPSD3234BV-24T6T
廠商: 意法半導體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core
中文描述: 閃存可編程系統(tǒng)設備與8032微控制器內核
文件頁數(shù): 158/170頁
文件大小: 2717K
代理商: UPSD3234BV-24T6T
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
158/170
Figure 83. Peripheral I/O READ Timing
Table 136. Port A Peripheral Data Mode READ Timing (5V Devices)
Note: 1. Any input used to select Port A Data Peripheral Mode.
2. Data is already stable on Port A.
Table 137. Port A Peripheral Data Mode READ Timing (3V Devices)
Note: 1. Any input used to select Port A Data Peripheral Mode.
2. Data is already stable on Port A.
Symbol
Parameter
Conditions
Min
Max
Turbo
Off
Unit
t
AVQV–PA
Address Valid to Data
Valid
(Note
1)
37
+ 10
ns
t
SLQV–PA
CSI Valid to Data Valid
27
+ 10
ns
t
RLQV–PA
RD to Data Valid
(Note
2)
32
ns
t
DVQV–PA
Data In to Data Out Valid
22
ns
t
RHQZ–PA
RD to Data High-Z
23
ns
Symbol
Parameter
Conditions
Min
Max
Turbo
Off
Unit
t
AVQV–PA
Address Valid to Data Valid
(Note
1)
50
+ 20
ns
t
SLQV–PA
CSI Valid to Data Valid
37
+ 20
ns
t
RLQV–PA
RD to Data Valid
(Note
2)
45
ns
t
DVQV–PA
Data In to Data Out Valid
38
ns
t
RHQZ–PA
RD to Data High-Z
36
ns
tRLQV (PA)
tDVQV (PA)
tRHQZ (PA)
tSLQV (PA)
tAVQV (PA)
ADDRESS
DATA VALID
ALE
A/D BUS
RD
DATA ON PORT A
CSI
AI06610
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uPSD3234BV-24U1T Flash Programmable System Devices with 8032 Microcontroller Core
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