參數(shù)資料
型號: uPSD3234B-24U6T
廠商: 意法半導體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core
中文描述: 閃存可編程系統(tǒng)設備與8032微控制器內(nèi)核
文件頁數(shù): 156/170頁
文件大?。?/td> 2717K
代理商: UPSD3234B-24U6T
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
156/170
Figure 82. Input Macrocell Timing (product term clock)
Table 132. Input Macrocell Timing (5V Devices)
Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to t
AVLX
and t
LXAX
.
Table 133. Input Macrocell Timing (3V Devices)
Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to t
AVLX
and t
LXAX
.
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Unit
t
IS
Input Setup Time
(Note
1)
0
ns
t
IH
Input Hold Time
(Note
1)
15
+ 10
ns
t
INH
NIB Input High Time
(Note
1)
9
ns
t
INL
NIB Input Low Time
(Note
1)
9
ns
t
INO
NIB Input to Combinatorial Delay
(Note
1)
34
+ 2
+ 10
ns
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Unit
t
IS
Input Setup Time
(Note
1)
0
ns
t
IH
Input Hold Time
(Note
1)
25
+ 20
ns
t
INH
NIB Input High Time
(Note
1)
12
ns
t
INL
NIB Input Low Time
(Note
1)
12
ns
t
INO
NIB Input to Combinatorial Delay
(Note
1)
46
+ 4
+ 20
ns
t
INH
t
INL
t
INO
t
IH
t
IS
PT CLOCK
INPUT
OUTPUT
AI03101
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