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參數(shù)資料
| 型號： | uPSD3234AV-40U6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash Programmable System Devices with 8032 Microcontroller Core |
| 中文描述： | 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核 |
| 文件頁數(shù)： | 112/170頁 |
| 文件大?。?/td> | 2717K |
| 代理商： | UPSD3234AV-40U6T |
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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
112/170
PLDS
The PLDs bring programmable logic functionality
to the uPSD. After specifying the logic for the
PLDs in PSDsoft Express, the logic is pro-
grammed into the device and available upon Pow-
er-up.
Table 90. DPLD and CPLD Inputs
Note: 1. These inputs are not available in the 52-pin package.
The PSD Module contains two PLDs: the Decode
PLD (DPLD), and the Complex PLD (CPLD). The
PLDs are briefly discussed in the next few para-
graphs, and in more detail in
Decode PLD
(DPLD), page 114
,
and
(CPLD), page 115
.
Figure 58., page 113
shows
the configuration of the PLDs.
The DPLD performs address decoding for Select
signals for PSD Module components, such as
memory, registers, and I/O ports.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the Out-
put Macrocells (OMC), Input Macrocells (IMC),
and the AND Array. The CPLD can also be used
to generate External Chip Select (ECS1-ECS2)
signals.
The AND Array is used to form product terms.
These product terms are specified using PSDsoft.
The PLD input signals consist of internal MCU sig-
nals and external inputs from the I/O ports. The in-
put signals are shown in Table
90
.
The Turbo Bit in PSD Module
The PLDs can minimize power consumption by
switching off when inputs remain unchanged for
an extended time of about 70ns. Resetting the
Turbo Bit to '0' (Bit 3 of PMMR0) automatically
places the PLDs into standby if no inputs are
changing. Turning the Turbo Mode off increases
propagation delays while reducing power con-
sumption.
See
POWER MANAGEMENT, page 128
, on how
to set the Turbo Bit.
Additionally, five bits are available in PMMR2 to
block MCU control signals from entering the PLDs.
This reduces power consumption and can be used
only when these MCU control signals are not used
in PLD logic equations.
Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.
Complex
PLD
Input Source
Input Name
Number
of
Signals
MCU Address Bus
A15-A0
16
MCU Control Signals
PSEN, RD, WR,
ALE
4
RESET
RST
1
Power-down
PDN
1
Port A Input
Macrocells
(1)
PA7-PA0
8
Port B Input
Macrocells
PB7-PB0
8
Port C Input
Macrocells
PC2-4, PC7
4
Port D Inputs
PD2-PD1
2
Page Register
PGR7-PGR0
8
Macrocell AB
Feedback
MCELLAB.FB7-
FB0
8
Macrocell BC
Feedback
MCELLBC.FB7-
FB0
8
Flash memory
Program Status Bit
Ready/Busy
1
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|---|---|
| uPSD3234B-24T1T | Flash Programmable System Devices with 8032 Microcontroller Core |
| uPSD3234B-24T6T | Flash Programmable System Devices with 8032 Microcontroller Core |
| uPSD3234B-24U1T | Flash Programmable System Devices with 8032 Microcontroller Core |
| uPSD3234B-24U6T | Flash Programmable System Devices with 8032 Microcontroller Core |
| uPSD3234B-40T1T | Flash Programmable System Devices with 8032 Microcontroller Core |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPSD3234B-24T1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3234B-24T1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core |
| UPSD3234B-24T6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3234B-24T6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core |
| UPSD3234B-24U1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
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