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參數(shù)資料
| 型號(hào)： | uPSD3234A-24T1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash Programmable System Devices with 8032 Microcontroller Core |
| 中文描述： | 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核 |
| 文件頁(yè)數(shù)： | 56/170頁(yè) |
| 文件大?。?/td> | 2717K |
| 代理商： | UPSD3234A-24T1T |
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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
56/170
STANDARD SERIAL INTERFACE (UART)
The uPSD323X Devices provides two standard
8032 UART serial ports. The first port is connected
to pin P3.0 (RX) and P3.1 (TX). The second port is
connected to pin P1.2 (RX) and P1.3(TX). The op-
eration of the two serial ports are the same and are
controlled by the SCON and SCON2 registers.
The serial port is full duplex, meaning it can trans-
mit and receive simultaneously. It is also receive-
buffered, meaning it can commence reception of a
second byte before a previously received byte has
been read from the register. (However, if the first
byte still has not been read by the time reception
of the second byte is complete, one of the bytes
will be lost.) The serial port receive and transmit
registers are both accessed at Special Function
Register SBUF (or SBUF2 for the second serial
port). Writing to SBUF loads the transmit register,
and reading SBUF accesses a physically separate
receive register.
The serial port can operate in 4 modes:
Mode 0.
Serial data enters and exits through
RxD. TxD outputs the shift clock. 8 bits are trans-
mitted/received (LSB first). The baud rate is fixed
at 1/12 the f
OSC
.
Mode 1.
10 bits are transmitted (through TxD) or
received (through RxD): a start Bit (0), 8 data bits
(LSB first), and a Stop Bit (1). On receive, the Stop
Bit goes into RB8 in Special Function Register
SCON. The baud rate is variable.
Mode 2.
11 bits are transmitted (through TxD) or
received (through RxD): start Bit (0), 8 data bits
(LSB first), a programmable 9th data bit, and a
Stop Bit (1). On Transmit, the 9th data bit (TB8 in
SCON) can be assigned the value of '0' or '1.' Or,
for example, the Parity Bit (P, in the PSW) could
be moved into TB8. On receive, the 9th data bit
goes into RB8 in Special Function Register SCON,
while the Stop Bit is ignored. The baud rate is pro-
grammable to either 1/32 or 1/64 the oscillator fre-
quency.
Mode 3.
11 bits are transmitted (through TxD) or
received (through RxD): a start Bit (0), 8 data bits
(LSB first), a programmable 9th data bit, and a
Stop Bit (1). In fact, Mode 3 is the same as Mode
2 in all respects except baud rate. The baud rate
in Mode 3 is variable.
In all four modes, transmission is initiated by any
instruction that uses SBUF as a destination regis-
ter. Reception is initiated in Mode 0 by the condi-
tion RI = 0 and REN = 1. Reception is initiated in
the other modes by the incoming start bit if REN =
1.
Multiprocessor Communications
Modes 2 and 3 have a special provision for multi-
processor communications. In these modes, 9
data bits are received. The 9th one goes into RB8.
Then comes a Stop Bit. The port can be pro-
grammed such that when the Stop Bit is received,
the serial port interrupt will be activated only if RB8
= 1. This feature is enabled by setting Bit SM2 in
SCON. A way to use this feature in multi-proces-
sor systems is as follows:
When the master processor wants to transmit a
block of data to one of several slaves, it first sends
out an address byte which identifies the target
slave. An address byte differs from a data byte in
that the 9th bit is '1' in an address byte and 0 in a
data byte. With SM2 = 1, no slave will be interrupt-
ed by a data byte. An ad-dress byte, however, will
interrupt all slaves, so that each slave can exam-
ine the received byte and see if it is being ad-
dressed. The addressed slave will clear its SM2
Bit and prepare to receive the data bytes that will
be coming. The slaves that weren’t being ad-
dressed leave their SM2s set and go on about
their business, ignoring the coming data bytes.
SM2 has no effect in Mode 0, and in Mode 1 can
be used to check the validity of the Stop Bit. In a
Mode 1 reception, if SM2 = 1, the receive interrupt
will not be activated unless a valid Stop Bit is re-
ceived.
Serial Port Control Register
The serial port control and status register is the
Special Function Register SCON (SCON2 for the
second port), shown in
Figure 27., page 61
. This
register contains not only the mode selection bits,
but also the 9th data bit for transmit and receive
(TB8 and RB8), and the Serial Port Interrupt Bits
(TI and RI).
Table 43. Serial Port Control Register (SCON)
7
6
5
4
3
2
1
0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| uPSD3234A-24T6T | Flash Programmable System Devices with 8032 Microcontroller Core |
| uPSD3234A-24U1T | Flash Programmable System Devices with 8032 Microcontroller Core |
| uPSD3234AV-24U1T | Flash Programmable System Devices with 8032 Microcontroller Core |
| uPSD3234AV-40U1T | Flash Programmable System Devices with 8032 Microcontroller Core |
| uPSD3234AV-40U6T | Flash Programmable System Devices with 8032 Microcontroller Core |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPSD3234A-24T6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3234A-24T6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| UPSD3234A-24U1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3234A-24U1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| UPSD3234A-24U6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
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