參數(shù)資料
型號： uPSD3233BV-40U6T
廠商： 意法半導體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core
中文描述： 閃存可編程系統(tǒng)設備與8032微控制器內核
文件頁數(shù)： 86/170頁
文件大?。?/td> 2717K
代理商： UPSD3233BV-40U6T
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
86/170
Table 72. Description of the UCON1 Bits
Table 73. USB Control Register (UCON2: 0ECh)
Table 74. Description of the UCON2 Bits
Table 75. USB Endpoint0 Status Register (USTA: 0EDh)
Bit
Symbol
R/W
Function
7
TSEQ1
R/W
Endpoint 1/ Endpoint 2 Transmit Data Packet PID. (0=DATA0, 1=DATA1)
This bit determines which type of data packet (DATA0 or DATA1) will be
sent during the next IN transaction directed to Endpoint 1 or Endpoint 2.
Toggling of this bit must be controlled by software. RESET clears this bit.
6
EP12SEL
R/W
Endpoint 1/ Endpoint 2 Transmit Selection. (0=Endpoint 1, 1=Endpoint 2)
This bit specifies whether the data inside the registers UDT1 are used for
Endpoint 1 or Endpoint 2. If all the conditions for a successful Endpoint 2
USB response to a hosts IN token are satisfied (TXD1F=0, TX1E=1,
STALL2=0, and EP2E=1) except that the EP12SEL Bit is configured for
Endpoint 1, the USB responds with a NAK handshake packet. RESET
clears this bit.
5
TX1E
R/W
Endpoint1 / Endpoint2 Transmit Enable.
This bit enables a transmit to occur when the USB Host Controller send
an IN token to Endpoint 1 or Endpoint 2. The appropriate endpoint
enable bit, EP1E or EP2E Bit in the UCON2 register, should also be set.
Software should set the TX1E Bit when data is ready to be transmitted. It
must be cleared by software when no more data needs to be transmitted.
If this bit is '0' or TXD1F is set, the USB will respond with a NAK
handshake to any Endpoint 1 or Endpoint 2 directed IN token.
RESET clears this bit.
4
FRESUM
R/W
Force Resume.
This bit forces a resume state (“K” on non-idle state) on the USB data
lines to initiate a remote wake-up. Software should control the timing of
the forced resume to be between 10ms and 15ms. Setting this bit will not
cause the RESUMF Bit to set.
3 to 0
TP1SIZ3 to
TP1SIZ0
R/W
The number of transmit data bytes. These bits are cleared by RESET.
7
6
5
4
3
2
1
0
—
—
—
SOUT
EP2E
EP1E
STALL2
STALL1
Bit
Symbol
R/W
Function
7 to 5
—
—
Reserved
4
SOUT
R/W
Status out is used to automatically respond to the OUT of a control
READ transfer
3
EP2E
R/W
Endpoint2 enable. RESET clears this bit
2
EP1E
R/W
Endpoint1 enable. RESET clears this bit
1
STALL2
R/W
Endpoint2 Force Stall Bit. RESET clears this bit
0
STALL1
R/W
Endpoint1 Force Stall Bit. RESET clears this bit
7
6
5
4
3
2
1
0
RSEQ
SETUP
IN
OUT
RP0SIZ3
RP0SIZ2
RP0SIZ1
RP0SIZ0
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相關代理商/技術參數(shù)
參數(shù)描述
UPSD32348V24V6ES 制造商:ST MICRO 功能描述:*
UPSD3234A 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
UPSD3234A-24T1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3234A-24T1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
UPSD3234A-24T6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
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