參數(shù)資料
型號: uPSD3233BV-40U1T
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core
中文描述: 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核
文件頁數(shù): 40/170頁
文件大?。?/td> 2717K
代理商: UPSD3233BV-40U1T
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
40/170
POWER-SAVING MODE
Two software selectable modes of reduced power
consumption are implemented.
Idle Mode
The following Functions are Switched Off.
CPU (Halted)
The following Function Remain Active During Idle
Mode.
External Interrupts
Timer 0, Timer 1, Timer 2
DDC Interface
PWM Units
USB Interface
USART
8-bit ADC
I
2
C Interface
Note:
Interrupt or RESET terminates the Idle
Mode.
Power-Down Mode
System Clock Halted
LVD Logic Remains Active
SRAM contents remains unchanged
The SFRs retain their value until a RESET is
asserted
Note:
The only way to exit Power-down Mode is a
RESET.
Table 25. Power-Saving Mode Power Consumption
Power Control Register
The Idle and Power-down Modes are activated by software via the PCON register.
Table 26. Pin Status During Idle and Power-down Mode
Table 27. Description of the PCON Bits
Note: 1. See the T2CON register for details of the flag description
Mode
Addr/Data
Ports1,3,4
PWM
I
2
C
DDC
USB
Idle
Maintain Data
Maintain Data
Active
Active
Active
Active
Power-down
Maintain Data
Maintain Data
Disable
Disable
Disable
Disable
SFR
Addr
Reg
Name
Bit Register Name
ValueComments
7
6
5
4
3
2
1
0
87
PCON
SMOD
SMOD1
LVREN ADSFINT RCLK1
TCLK1
PD
IDLE
00
Power Ctrl
Bit
Symbol
Function
7
SMOD
Double baud data rate bit UART
6
SMOD1
Double baud data rate bit 2nd UART
5
LVREN
LVR disable bit (active High)
4
ADSFINT
Enable ADC Interrupt
3
RCLK1
(1)
Received clock flag (UART 2)
2
TCLK1
(1)
Transmit clock flag (UART 2)
1
PD
Activate Power-down Mode (High enable)
0
IDL
Activate Idle Mode (High enable)
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