參數(shù)資料
型號: uPSD3233BV-40T6T
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core
中文描述: 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核
文件頁數(shù): 159/170頁
文件大?。?/td> 2717K
代理商: UPSD3233BV-40T6T
159/170
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Figure 84. Peripheral I/O WRITE Timing
Table 138. Port A Peripheral Data Mode WRITE Timing (5V Devices)
Note: 1. Data stable on Port 0 pins to data on Port A.
Table 139. Port A Peripheral Data Mode WRITE Timing (3V Devices)
Note: 1. Data stable on Port 0 pins to data on Port A.
Symbol
Parameter
Conditions
Min
Max
Unit
t
WLQV–PA
WR to Data Propagation Delay
25
ns
t
DVQV–PA
Data to Port A Data Propagation Delay
(Note
1)
22
ns
t
WHQZ–PA
WR Invalid to Port A Tri-state
20
ns
Symbol
Parameter
Conditions
Min
Max
Unit
t
WLQV–PA
WR to Data Propagation Delay
42
ns
t
DVQV–PA
Data to Port A Data Propagation Delay
(Note
1)
38
ns
t
WHQZ–PA
WR Invalid to Port A Tri-state
33
ns
tDVQV (PA)
tWLQV (PA)
tWHQZ (PA)
ADDRESS
DATA OUT
A/D BUS
WR
PORT A
DATA OUT
ALE
AI06611
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