參數(shù)資料
型號(hào)： UPI-452
廠商： Intel Corp.
英文描述： CHMOS PROGRAMMABLE I/O PROCESSOR
中文描述： CHMOS可編程I / O處理器
文件頁(yè)數(shù)： 1/53頁(yè)
文件大?。?/td> 499K
代理商： UPI-452
*
Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
November 1994
COPYRIGHT
INTEL CORPORATION, 1996
Order Number: 231428-006
UPI-452
CHMOS PROGRAMMABLE I/O PROCESSOR
83C452 - 8K
c
8 Mask Programmable Internal ROM
80C452 - External ROM/EPROM
Y
83C452/80C452:3.5 to 14 MHz Clock
Rate
Y
Software Compatible with the MCS-51
Family
Y
128-Byte Bi-Directional FIFO Slave
Interface
Y
Two DMA Channels
Y
256
c
8-Bit Internal RAM
Y
34 Additional Special Function
Registers
Y
40 Programmable I/O Lines
Y
Two 16-Bit Timer/Counters
Y
Boolean Processor
Y
Bit Addressable RAM
Y
8 Interrupt Sources
Y
Programmable Full Duplex Serial
Channel
Y
64K Program Memory Space
Y
64K Data Memory Space
Y
68-Pin PGA and PLCC
(See Packaging Spec., Order:
Y
231369)
The Intel UPI-452 (Universal Peripheral Interface) is a 68 pin CHMOS Slave I/O Processor with a sophisticated
bi-directional FIFO buffer interface on the slave bus and a two channel DMA processor on-chip. The UPI-452
is the newest member of Intel’s UPI family of products. It is a general-purpose slave I/O Processor that allows
the designer to grow a customized interface solution.
The UPI-452 contains a complete 80C51 with twice the on-chip data and program memory. The sophisticated
slave FIFO module acts as a buffer between the UPI-452 internal CPU and the external host CPU. To both the
external host and the internal CPU, the FIFO module looks like a bi-directional bottomless buffer that can both
read and write data. The FIFO manages the transfer of data independent of the UPI-452 core CPU and
generates an interrupt or DMA request to either CPU, host or internal, as a FIFO service request.
The FIFO consists of two channels:the Input FIFO and the Output FIFO. The division of the FIFO module
array, 128 bytes, between Input channel and Output channel is programmable by the user. Each FIFO byte
has an additional logical ninth bit to distinguish between a data byte and a Data Stream Command byte.
Additionally, Immediate Commands allow direct, interrupt driven, bi-directional communication between the
UPI-452 internal CPU and external host CPU, bypassing the FIFO.
The on-chip DMA processor allows high speed data transfers from one writeable memory space to another.
As many as 64K bytes can be transferred in a single DMA operation. Three distinct memory spaces may be
used in DMA operations; Internal Data Memory, External Data Memory, and the Special Function Registers
(including the FIFO IN, FIFO OUT, and Serial Channel Special Functions Registers).
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