參數(shù)資料
型號: UPD78P4038YGK
廠商: NEC Corp.
英文描述: RECTIFIER BRIDGE 2A 50V 65A-ifsm 1.1V-vf 5uA-ir KBP 35/TUBE
中文描述: 16/8-BIT單片機(jī)
文件頁數(shù): 36/72頁
文件大?。?/td> 435K
代理商: UPD78P4038YGK
μ
PD78P4038Y
36
(1) Read/write operation (2/2)
Note
The hold time includes the time during which V
OH1
and V
OL1
are held under the load conditions of
C
L
= 50 pF and R
L
= 4.7 k
.
Remarks
T:
t
CYK
(system clock cycle time)
Number of wait states (n
0)
n:
(2) Bus hold timing
Remarks
T:
t
CYK
(system clock cycle time)
1 (during address wait), otherwise, 0
Number of wait states (n
0)
a:
n:
Unit
ns
ns
ns
ns
ns
ns
ns
Parameter
Data setup time (to WR
)
Data hold time (to WR
)
Note
Delay from WR
to ASTB
WR low-level width
Symbol
t
SODW
t
HWOD
t
DWST
t
WWL
MIN.
(1.5 + n) T – 30
(1.5 + n) T – 40
0.5T – 5
0.5T – 25
0.5T – 12
(1.5 + n) T – 30
(1.5 + n) T – 40
MAX.
Conditions
V
DD
= +5.0 V
±
10%
V
DD
= +5.0 V
±
10%
V
DD
= +5.0 V
±
10%
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Delay from HLDRQ
to float
Delay from HLDRQ
to HLDAK
Delay from float to HLDAK
Delay from HLDRQ
to HLDAK
Delay from HLDAK
to active
MIN.
1T – 20
1T – 30
MAX.
(6 + a + n) T + 50
(7 + a + n) T + 30
(7 + a + n) T + 40
1T + 30
2T + 40
2T + 60
Conditions
V
DD
= +5.0 V
±
10%
V
DD
= +5.0 V
±
10%
V
DD
= +5.0 V
±
10%
Symbol
t
FHQC
t
DHQHHAH
t
DCFHA
t
DHQLHAL
t
DHAC
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