參數(shù)資料
型號: UPD78F9222MC-5A4-A
廠商: Renesas Electronics America
文件頁數(shù): 56/125頁
文件大?。?/td> 0K
描述: MCU 8BIT 4KB FLASH 20PIN
標準包裝: 400
系列: 78K0S/Kx1+
核心處理器: 78K0S
芯體尺寸: 8-位
速度: 10MHz
連通性: LIN,UART/USART
外圍設備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 15
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據轉換器: A/D 4x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-LSSOP(0.240",6.10mm 寬)
包裝: 托盤
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U16898EJ6V0UD
34
3.2
Processor Registers
The 78K0S/KA1+ provides the following on-chip processor registers.
3.2.1 Control registers
The control registers have special functions to control the program sequence statuses and stack memory. The
control registers include a program counter, a program status word, and a stack pointer.
(1) Program counter (PC)
The program counter is a 16-bit register which holds the address information of the next program to be
executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to
be fetched. When a branch instruction is executed, immediate data or register contents are set.
Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program
counter.
Figure 3-7. Program Counter Configuration
0
15
PC14
PC15
PC
PC13 PC12 PC11 PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.
Program status word contents are stored in stack area upon interrupt request generation or PUSH PSW
instruction execution and are restored upon execution of the RETI and POP PSW instructions.
Reset signal generation sets PSW to 02H.
Figure 3-8. Program Status Word Configuration
70
IE
Z
0
AC
0
1
CY
PSW
(a) Interrupt enable flag (IE)
This flag controls interrupt request acknowledge operations of the CPU.
When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests are disabled.
When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with
an interrupt mask flag for various interrupt sources.
This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases.
(c) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all
other cases.
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