參數(shù)資料
型號: UPD78F4216AGC-8EU
廠商: NEC Corp.
英文描述: MOS INTEGRATED CIRCUIT
中文描述: 馬鞍山集成電路
文件頁數(shù): 36/60頁
文件大?。?/td> 349K
代理商: UPD78F4216AGC-8EU
Data Sheet U14125EJ1V0DS00
36
μ
PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
(d) I
2
C bus mode
Standard Mode
High-Speed Mode
Parameter
Symbol
MIN.
MAX.
MIN.
MAX.
Unit
SCL0 clock frequency
f
CLK
0
100
0
400
kHz
Bus free time (between stop
and start conditions)
t
BUF
4.7
1.3
μ
s
Hold time
Note1
t
HD : STA
4.0
0.6
μ
s
Low-level width of SCL0 clock
t
LOW
4.7
1.3
μ
s
High-level width of SCL0 clock
t
HIGH
4.0
0.6
μ
s
Setup time of start/restart
conditions
t
SU : STA
4.7
0.6
μ
s
When using CBUS-
compatible master
5.0
μ
s
Data hold
time
When using I
2
C bus
t
HD : DAT
0
Note 2
0
Note 2
0.9
Note 3
μ
s
Data setup time
t
SU : DAT
250
100
Note 4
ns
Rise time of SDA0 and SCL0
signals
t
R
1,000
20 + 0.1Cb
Note 5
300
ns
Fall time of SDA0 and SCL0
signals
t
F
300
20 + 0.1Cb
Note 5
300
ns
Setup time of stop condition
t
SU : STO
4.0
0.6
μ
s
Pulse width of spike restricted
by input filter
t
SP
0
50
ns
Load capacitance of each bus
line
Cb
400
400
pF
Notes 1.
For the start condition, the first clock pulse is generated after the hold time.
2.
To fill the undefined area of the SCL0 falling edge, it is necessary for the device to provide an internal
SDA0 signal (on V
IHmin.
) with at least 300 ns of hold time.
3.
If the device does not extend the SCL0 signal low-level hold time (t
LOW
), only the maximum data hold
time t
HD : DAT
needs to be satisfied.
4.
The high-speed mode I
2
C bus can be used in a standard mode I
2
C bus system. In this case, the
conditions described below must be satisfied.
If the device does not extend the SCL0 signal low-level hold time
t
SU : DAT
250 ns
If the device extends the SCL0 signal low-level hold time
Be sure to transmit the data bit to the SDA0 line before the SCL0 line is released (t
Rmax.
+ t
SU :
DAT
= 1,000 + 250 = 1,250 ns by standard mode I
2
C bus specification)
5.
Cb: Total capacitance per bus line (unit: pF)
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