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CHAPTER 14 SERIAL INTERFACE IICA
User’s Manual U19678EJ1V1UD
788
14.5.7 Canceling wait
The I
2C usually cancels a wait state by the following processing.
Writing data to IICA shift register (IICA)
Setting bit 5 (WREL) of IICA control register 0 (IICCTL0) (canceling wait)
Setting bit 1 (STT) of IICCTL0 register (generating start condition)Note
Setting bit 0 (SPT) of IICCTL0 register (generating stop condition)Note
Note
Master only
When the above wait canceling processing is executed, the I
2C cancels the wait state and communication is
resumed.
To cancel a wait state and transmit data (including addresses), write the data to IICA.
To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WREL) of IICA control
register 0 (IICCTL0) to 1.
To generate a restart condition after canceling a wait state, set bit 1 (STT) of IICCTL0 to 1.
To generate a stop condition after canceling a wait state, set bit 0 (SPT) of IICCTL0 to 1.
Execute the canceling processing only once for one wait state.
If, for example, data is written to IICA after canceling a wait state by setting WREL to 1, an incorrect value may be
output to SDA0 because the timing for changing the SDA0 line conflicts with the timing for writing IICA.
In addition to the above, communication is stopped if IICE is cleared to 0 when communication has been aborted,
so that the wait state can be canceled.
If the I
2C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LREL) of
IICCTL0, so that the wait state can be canceled.
Caution
If a processing to cancel a wait state is executed when WUP = 1, the wait state will not be
canceled.