![](http://datasheet.mmic.net.cn/Renesas-Electronics-America/UPD78F1178AGF-GAT-AX_datasheet_99858/UPD78F1178AGF-GAT-AX_933.png)
APPENDIX B LIST OF CAUTIONS
User’s Manual U18432EJ5V0UD
931
(19/35)
Chapter
Classification
Function
Details of
Function
Cautions
Page
ISC: Input switch
control register
Be sure to clear bits 7 to 2 to “0”.
p.436
Registers
controlling
serial array
unit
NFEN0: Noise
filter enable
register 0
Be sure to clear bits 7, 5, 3, and 1 to “0”.
p.437
Operation
stop mode
Stopping the
operation by
units
If SAUmEN = 0, writing to a control register of serial array unit m is ignored, and,
even if the register is read, only the default value is read (except for input switch
control register (ISC), noise filter enable register (NFEN0), port input mode registers
(PIM0, PIM4, PIM9, PIM12, PIM14), port output mode registers (POM0, POM4,
POM9, POM12, POM14), port mode registers (PM0, PM1, PM4, PM9, PM12, PM14),
and port registers (P0, P1, P4, P9, P12, P14)).
p.441
pp.447
Master
transmission
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
451, 453
Master transmission
(in continuous
transmission mode)
The MDmn0 bit can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten
before the transfer end interrupt of the last transmit data.
p.452
pp.456,
Master reception After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
459, 461
Master reception
(in continuous
reception mode)
The MDmn0 bit can be rewritten even during operation.
However, rewrite it before receive of the last bit is started, so that it has been
rewritten before the transfer end interrupt of the last receive data.
p.460
pp.464,
Master
transmission/
reception
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
467, 469
Master
transmission/
reception (in
continuous
transmission/
reception mode)
The MDmn0 bit can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it has been
rewritten before the transfer end interrupt of the last transmit data.
p.468
pp.472,
Slave
transmission
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
476, 478
Slave transmission
(in continuous
transmission mode)
The MDmn0 bit can be rewritten even during operation. However, rewrite it before
transfer of the last bit is started.
p.477
Slave reception
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
pp.481,
484
pp.486,
Be sure to set transmit data to the SlOp register before the clock from the master is
started.
487, 489,
491, 493
pp.487,
Slave
transmission/
reception
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
491, 493
3-wire serial I/O
(CSI00, CSI01,
CSI10, CSI11,
CSI20, CSI21)
communication
Slave
transmission/
reception (in
continuous
transmission/
reception mode)
The MDmn0 bit can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten
before the transfer end interrupt of the last transmit data.
p.492
When using serial array units 0 and 1 as UARTs, the channels of both the
transmitting side (even-number channel) and the receiving side (odd-number
channel) can be used only as UARTs.
p.497
pp.501,
Chapter
1
3
Soft
UART (UART0,
UART1,
UART2,
UART3)
communication
UART
transmission
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
505